[kernel][pmm] change pmm single page alloc routines to return status

Move from returning a status and the page pointer and/or physical
address in an argument.

Tested: build and runtests on both x86 and arm

Change-Id: If10d877f152d355bfa1359338cd71f5aefbccfb4

[mmu][hypervisor] Support for more memory types

Add support for uncached, uncached device, and write-combining to
stage-2 page tables on arm64 and EPT page tables on x86-64.

Test: Ran 'guest launch zircon_guest', 'hypervisor-test',
'machina_unittests', and 'k ut hypervisor'.
Change-Id: I9d8e55c8357384e04a099c1cb25ac977027ed239

[arm64] Convert stage 2 PTE attributes to MMU flags

ZX-2211 #done

Change-Id: Ie5c6223962733a75ebf917691ebadb1c498da067

[kernel][kaslr] Create static relocation

Add static relocation for x64 and arm64 using the kernel_relocated_base
global variable. Add the DISABLE_KASLR option. Remove any dependency to
KERNEL_BASE when __code_start should be used. Change symbolize script to
dump kaslr offset and correctly show static addresses. Adapt gdb script
to identify KASLR relocation at early boot or if attached later.

x64 specific:
- Simplify page table to use kernel_relocated_base
- Fix zedboot and multiboot dependencies on the static kernel base
- Ensure 16-bit boot path is relocated for secondary CPUs

SEC-31 #comment Add static relocation of the kernel module

Change-Id: I9acb0a53a82c2bbf9973921e4cfe60a1e03c7006

[kernel][pmm] first pass overhaul of the PMM

-Add a new PmmNode class that represents a pmm for a single NUMA node.
-Move main free queues into PmmNode.
-Make PmmArena be a child of PmmNode.
-Refactor the vm_page structure a bit to change how queues work. Make
the main queue node be intrinsic to the page, instead of per state.
-Move some per page helper routines into the page struct.
-Remove the KMAP flags, since they're not used on 64bit machines.

TODO:
-Make use of the LO_MEM flag for <4GB allocations
-Make use of the new active/inactive/wired queues in PmmNode
-Add support for multiple nodes in a NUMA system
-Keep page state count in PmmNode class to make page state counting less
expensive

Change-Id: I0ca5e55aad0bb2f393d2dc590b02f160e4740398

[kernel][pmm] remove users of pmm_alloc_kpage

This is to help with an upcoming restructure of the way pages are
allocated from the pmm.
There wasn't much gain from using this convenience routine as it
currently stands.
Also remove the logic on the arm mmu code to allocate non page sized
page tables, which we currently dont support.

Change-Id: I7c834a7e3f4e8d2a3e73be8b092c9ccb9831b675

[kernel][arm64][mmu] add new cache type to closely map to the existing write combining type

ARM64 normal memory uncached most closely lines up with the existing
ARCH_MMU_FLAG_WRITE_COMBINING, which was previously just being mapped to
uncached.

Currently can't get to this yet, but wire up the underlying mmu bits so
we can take advantage of it in a future patch.

Change-Id: I33b838ec2429074ad82fb14d51f80bb305c9e118

[arm64][hypervisor] Simplify use of el2_tlbi_ipa

Move the shifting logic into arm64_el2_tlbi_ipa so that it can be easily
used elsewhere. Also invalidate all stage-1 translations when we
invalidate a stage-2.

Change-Id: If352efb897aadbd23d687c2ea1fa5c4a84c1936a

[arm64][mmu] Support TLBI of terminal stage-2 PTE

This matches the recent changes to the arm64 MMU code.

Change-Id: Iaea5c311f121744aac1511e317d8ab7d59d36dae

[kernel][arm64] clang format arm64 code

Change-Id: Id4b2123b16549c555db28bc878dde434f4dc5506

[kernel][arm64][mmu] refactor the asid allocator

Switch to a linear search instead of randomly picking a value.

Could degenerate to a slow algorithm, but practically speaking it will
generally allocate on the first attempt.

Change-Id: Ie01647910d86a24c65aa9e9c2fcba18c9f974a09

[kernel][arm64][mmu] refactor more code to use MmuParamsFromFlags()

Change-Id: Ie8dc03736fc9524636cdfb2f6001043fcba55a64

[kernel][arm64][mmu] pass less info into the inner routines

asid_ and tt_virt_ can be read from the inner routine, so don't pass
them through.

Change-Id: I1d305df2cd33b62da0a09d2146a3d4cace77ac25

[kernel][arm][mmu] properly flush when disconnecting inner page tables

Consolidate TLB flushing into a single routine that selects the proper
tlb flush instruction based on it being an inner or terminal flush
operation.

Change-Id: I47bc07c3046eceee23db12289c1663697e9f74e3

[kernel][arm64] tighten up memory barriers and sync barriers in the mmu code

-Move most DSB SY to the slightly weaker DSB ISHST, since inner shared
domain is all that is necessary to sync pending TLB instructions and
memory updates with the page walker.
-Add some higher level macros for the two DSB/DMB variants we care
about.

Change-Id: Iaa6c044060dea950925c139cc46b923a0bdddf02

[kernel][arm64][mmu] add some ktrace probes

Change-Id: I54a6468f0173de3c7577743106bea52b13ceb563

[kernel][arm64][mmu] only use pmm_alloc_contiguous if the requested size > PAGE_SIZE

This avoids unnecessarily calling pmm_alloc_contiguous, which is much
slower by default than a regular page alloc.

Change-Id: I2c34fcf846df7f0c3deaa6984c27e5335ac93b91

[kernel][mmu] Fix typo'd DEBUG_ASSERT condition

This failed into "(x & 0) == 0" check.

Change-Id: I59c355c2ff924058bcb993236f327fd42c5656a3

[arm64][mmu] Use lock annotations and RAII mutex in mmu code

Change-Id: I4f17422389c6e2f11e90426be3d5432ae4a49911

[kernel] remove most uses of MEMBASE + KERNEL_LOAD_OFFSET

These two variables are almost always used when code wants to know the
kernel's physical load address. Add some code to simply save the kernel
load location at boot time and use that instead.
Also standardized the use of linker script defined variables into a
common header and format.

Change-Id: Iccde557d1082d39167a53b0fdc5f23289d81f200

[kernel][arm] update the boot-mmu code to handle large pages and being used after the kernel has gone virtual

Change-Id: Ifa0eef2c70d92fd7c225c8a123aa32391b30d198

[arch][mmu] Define and implement non-contiguous Map function

ZX-1424 #comment initial functionality in, need some callers

Change-Id: I98cf351bfc7cbc5665e94688fabc53c7fde3f452

[arch][mmu] Rename Map to MapContiguous

This is prep work for adding support for adding a non-contiguous map.

ZX-1424

Change-Id: I63a557a884cfe496cfee2fa58e9f9ec17ba18b8e

[arm][hypervisor] Fix handling of TLBI in EL2.

We should be using the proper value of VTTBR_EL2 when switching to the
guest in order to execute TLBI. Previously we were incorrectly using the
VMID, without combining it with the translation table address.

ZX-1347 #comment

Change-Id: I0fd3c4d291868ec0b4166e601d8be8f81cb75dfd

[kernel][memory] refactor some physical<->virtual routines, formally naming the BKM physmap

This mostly just rearranges the names of things, but add an actual name
for the big kernel map and add some bounds checking to usage.

This should let us be a bit more dynamic about the physmap in the
future, including placing it at a random location and/or giving it a
more complex mapping.

Change-Id: I062d3f0483f27436252b9607174e10b852f0f832

[arm64][hypervisor] Add TLB invalidation of guest.

Invalidate the TLB when modifying the guest physical address space PTEs.

ZX-1277 #done

Change-Id: I05d72850d7b54be53e8b98c65abd6c316c03bbf1

[kernel][arm64] read the icache and dcache line size at boot and use for cache routines

Previously was hard coded at 64. This should help us run on machines
with different sized cache lines.

Change-Id: I751d066278ecd8159142583bfa400a828021d50e

[arm64] Always use normal memory for stage 2 PTEs.

The hypervisor requires the use of normal memory to operate correctly on
hardware.

Also only set the non-global bit for stage 1 PTEs.

ZX-1241 #comment

Change-Id: I8e7cf49027473dc5afcb6b923ce5d9f42c24eca2

[kernel][arm64] move bss initialization earlier, remove prebss

-Turns out we were already initializing the data cache early on, so
there's no real downside to zeroing out bss on the first cpu just after
enabling data cache but before setting up in the mmu.

Change-Id: Iad3f6e0b8a78ddaf4b627673264053c717635190

[arm64][mmu] Correctly set S2 PTE attributes.

Stage 2 level 3 PTEs have a different attribute format to stage 1 PTEs.
We need to correctly set them for use with the hypervisor.

ZX-1241 #comment In Progress

Change-Id: Icfec1194a7c9dac0673c344f12f6244c71ff1900

[arm64][mmu] Add support for guest aspace.

Due to the way VTCR_EL2 is dependent upon ID_AA64MMFR0_EL1.PARange, and
the fact that PARange is limited to 40-bits on Cortex-A53, we can't use
the same configuration as the user-space mappings for guest mappings.

This change adds the basic setup for handling guest mappings, but
doesn't contain the TLBI operations needed. Those will come in a follow
up.

Change-Id: I9538ccc81a2c3d4afd141d2e28d3196a967fc370

[kernel][status][arch] Use zx_status_t throughout kernel/arch

Change-Id: I051aaaee84c6e7776b0054171f8d69320d812fcb

[kernel][vm] move vm.h to the new spot and remove some unused code

Change-Id: I69f1b804fb95dd44e3e0619943e8809519aa82ca

[zx] Magenta -> Zircon

The Great Renaming is here!

Change-Id: I3229bdeb2a3d0e40fb4db6fec8ca7d971fbffb94

[zircon][mxtl->fbl] Rename mxtl to fbl

Change-Id: Ie21b6498e1bfb0a7fa0315e40b9e5c3ee78646be

[kernel][vm] move kernel/kernel/vm to just kernel/vm

Change-Id: I8f724a9f8a61415712661d1fdd3dc4e1c70cf620

[kernel][mmu] add a mutex to the low level mmu classes

There's at least one scenario in the high level vm that allows for concurrent
access to the low level mmu code: a simultaneous unmap and decommit on
the same vmo.

MG-1041 #done

Change-Id: Id360e19068ccddffd2db1515024a9b5d959d77f4

[kernel] Replace CF with atomic_signal_fence()

Change-Id: Ib6a98316fa67ddf2ea8c9c84ca29bef621f23c7d

[kernel][vm][arm] Remove arch_aspace_t.

Change-Id: Ia23461f1c8b41bd422e2d3e961809fe654e12fb1

[kernel][mmu] account for page tables per aspace

MG-875 #done

Change-Id: I6ea5308405bd192ada2f10d7be650c943b40d4e9

[kernel][vm] Implement {X86|Arm}ArchVmAspace.

Add distinct ArchVmAspace implementations for each architecture and
convert the old 'arch_mmu_*' functions to use static linkage.

VmAspace still resolves to a single ArchVmAspace implementation at
compile-time.

Change-Id: I347ec0d88634295fd5945c7a72c2f950a6053fdc

[kernel][vm] objectify the mmu layer by adding a simple wrapper object

This just adds a wrapper object around the arch_mmu routines and
switches the high level api to an object oriented model. Subsequent
changes will remove the wrapper and have the two arches implement the
objects directly.

Change-Id: I5ce0d28db5612f4fbc9e0c87d2f6b22dcd09a3f1

[kernel][arch][arm64] Use the new MX_OK and MX_ERR_* names

Change-Id: I1e3a720d37f48c73356fadd0a1317b8ec249ceba

[kernel][vm] restructure kernel vm headers and remove more legacy routines

Mostly unpack vm.h into a few separate headers.

No functional change

Change-Id: Ifd85506f49596d82a3a0e970fc911a34f3064d70

[arm64][mmu] Mark PT accesses as volatile

Change-Id: I5942884961602916185337a121ca5c34be2e64e3

[kernel][mmu] switch the low level mmu api to returning status_t instead of int

In the case of map/unmap, optionally return the count of pages mapped/unmapped.

Change-Id: I216b030c309b4a457688bedb1ce4bf99359f94d3

[kernel][arm64] clang format the arm64 mmu code

Change-Id: I2db328bbaf457c1772c9f39d744da9291a69c35e

[kernel][arm64] flip the arm64 mmu code from C to C++

Just a trivial change to get it to compile and work, not a complete refactor.
That will come in an upcoming change to switch to an OO model.

Change-Id: I81167a53e435df37fe3d2d7c0ad810f04b08c33b