powerpc/mpc85xx/pci_fdt.c

327 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
337 	addr |= (slot & 0x1f) << 11;
368 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
378 	addr |= (slot & 0x1f) << 11;
443 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
449 	if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
451 	devfn = DEVFN(bus, slot, func);
456 	return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
460 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
465 	if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
467 	fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
472     int slot, int fn)
476 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1);
477 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1);
478 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1);
479 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1);
481 		sc->sc_devfn_via_ide = DEVFN(bus, slot, fn);
482 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1);
487 fsl_pcib_init_bar(struct fsl_pcib_softc *sc, int bus, int slot, int func,
496 	if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) {
505 		fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
509 	fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
510 	size = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
535 		    device_get_unit(sc->sc_dev), bus, slot, func, reg,
538 	fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
540 		fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
546 fsl_pcib_route_int(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
554 	devfn = DEVFN(bus, slot, func);
563 			err = fdt_pci_route_intr(bus, slot, func, intpin,
571 		    unit, bus, slot, func, intpin, intline);
582 	int slot, func, maxfunc;
589 	for (slot = 0; slot <= maxslot; slot++) {
592 			hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot,
601 			vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot,
603 			device = fsl_pcib_read_config(sc->sc_dev, bus, slot,
607 				sc->sc_devfn_tundra = DEVFN(bus, slot, func);
611 			command = fsl_pcib_read_config(sc->sc_dev, bus, slot,
614 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
618 				fsl_pcib_init_via(sc, device, bus, slot, func);
624 				bar += fsl_pcib_init_bar(sc, bus, slot, func,
628 			intpin = fsl_pcib_read_config(sc->sc_dev, bus, slot,
630 			intline = fsl_pcib_route_int(sc, bus, slot, func,
632 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
636 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
642 			class = fsl_pcib_read_config(sc->sc_dev, bus, slot,
644 			subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
656 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
658 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
660 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
662 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
666 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
668 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
672 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
674 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
676 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
678 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
683 			    slot, func, PCIR_PRIBUS_1, 1);
685 			    slot, func, PCIR_SECBUS_1, 1);
687 			    slot, func, PCIR_SUBBUS_1, 1);
708 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
710 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
712 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,