Lines Matching refs:hw
42 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
43 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
44 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
45 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
46 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
47 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
48 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
49 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
52 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
55 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
57 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
58 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
59 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
60 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
62 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
63 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
64 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
65 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
66 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
67 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
68 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
69 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
70 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
72 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
74 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
75 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
76 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
77 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
78 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
93 * @hw: pointer to the HW structure
95 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
97 struct e1000_phy_info *phy = &hw->phy;
102 if (hw->phy.media_type != e1000_media_type_copper) {
133 ret_val = e1000_get_phy_id(hw);
147 * @hw: pointer to the HW structure
149 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
151 struct e1000_nvm_info *nvm = &hw->nvm;
152 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
204 * @hw: pointer to the HW structure
206 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
208 struct e1000_mac_info *mac = &hw->mac;
213 switch (hw->device_id) {
215 hw->phy.media_type = e1000_media_type_internal_serdes;
221 hw->phy.media_type = e1000_media_type_copper;
237 mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) &
248 /* hw initialization */
279 hw->mac.ops.set_lan_id(hw);
286 * @hw: pointer to the HW structure
290 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
294 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
295 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
296 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
301 * @hw: pointer to the HW structure
305 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
311 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
312 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
317 * @hw: pointer to the HW structure
321 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
327 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
328 e1000_release_swfw_sync_80003es2lan(hw, mask);
333 * @hw: pointer to the HW structure
338 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
346 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
351 * @hw: pointer to the HW structure
355 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
363 e1000_release_swfw_sync_80003es2lan(hw, mask);
368 * @hw: pointer to the HW structure
372 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
378 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
382 ret_val = e1000_acquire_nvm_generic(hw);
385 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
393 * @hw: pointer to the HW structure
397 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
401 e1000_release_nvm_generic(hw);
402 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
407 * @hw: pointer to the HW structure
413 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
424 if (e1000_get_hw_semaphore_generic(hw)) {
429 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
437 e1000_put_hw_semaphore_generic(hw);
449 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
451 e1000_put_hw_semaphore_generic(hw);
459 * @hw: pointer to the HW structure
465 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
471 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
474 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
476 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
478 e1000_put_hw_semaphore_generic(hw);
483 * @hw: pointer to the HW structure
489 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
498 ret_val = e1000_acquire_phy_80003es2lan(hw);
514 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
516 e1000_release_phy_80003es2lan(hw);
520 if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) {
529 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
533 e1000_release_phy_80003es2lan(hw);
539 ret_val = e1000_read_phy_reg_mdic(hw,
545 ret_val = e1000_read_phy_reg_mdic(hw,
550 e1000_release_phy_80003es2lan(hw);
558 * @hw: pointer to the HW structure
564 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
573 ret_val = e1000_acquire_phy_80003es2lan(hw);
589 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
591 e1000_release_phy_80003es2lan(hw);
595 if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) {
604 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
608 e1000_release_phy_80003es2lan(hw);
614 ret_val = e1000_write_phy_reg_mdic(hw,
620 ret_val = e1000_write_phy_reg_mdic(hw,
625 e1000_release_phy_80003es2lan(hw);
633 * @hw: pointer to the HW structure
640 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
645 return e1000_write_nvm_spi(hw, offset, words, data);
650 * @hw: pointer to the HW structure
655 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
663 if (hw->bus.func == 1)
667 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
684 * @hw: pointer to the HW structure
689 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
697 if (!(hw->phy.ops.read_reg))
704 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
709 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
715 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
719 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
724 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
730 if (hw->phy.autoneg_wait_to_complete) {
733 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
743 ret_val = e1000_phy_reset_dsp_generic(hw);
749 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
755 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
765 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
775 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
784 * @hw: pointer to the HW structure
789 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
791 struct e1000_phy_info *phy = &hw->phy;
797 if (!(hw->phy.ops.read_reg))
800 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
822 * @hw: pointer to the HW structure
828 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
835 if (hw->phy.media_type == e1000_media_type_copper) {
836 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
838 hw->phy.ops.cfg_on_link_up(hw);
840 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
850 * @hw: pointer to the HW structure
854 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
865 ret_val = e1000_disable_pcie_master_generic(hw);
870 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
872 E1000_WRITE_REG(hw, E1000_RCTL, 0);
873 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
874 E1000_WRITE_FLUSH(hw);
878 ctrl = E1000_READ_REG(hw, E1000_CTRL);
880 ret_val = e1000_acquire_phy_80003es2lan(hw);
882 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
883 e1000_release_phy_80003es2lan(hw);
885 ret_val = e1000_get_auto_rd_done_generic(hw);
891 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
892 E1000_READ_REG(hw, E1000_ICR);
894 ret_val = e1000_check_alt_mac_addr_generic(hw);
902 * @hw: pointer to the HW structure
904 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
906 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
908 struct e1000_mac_info *mac = &hw->mac;
916 e1000_initialize_hw_bits_80003es2lan(hw);
919 ret_val = mac->ops.id_led_init(hw);
926 mac->ops.clear_vfta(hw);
929 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
934 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
937 ret_val = mac->ops.setup_link(hw);
940 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
943 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
947 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
950 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
953 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
956 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
959 reg_data = E1000_READ_REG(hw, E1000_TCTL);
961 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
964 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
967 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
970 reg_data = E1000_READ_REG(hw, E1000_TIPG);
973 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
975 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
977 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
980 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
982 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
989 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE;
998 e1000_clear_hw_cntrs_80003es2lan(hw);
1004 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
1005 * @hw: pointer to the HW structure
1009 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
1016 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1018 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1021 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1023 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1026 reg = E1000_READ_REG(hw, E1000_TARC(0));
1028 if (hw->phy.media_type != e1000_media_type_copper)
1030 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1033 reg = E1000_READ_REG(hw, E1000_TARC(1));
1034 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1038 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1045 * @hw: pointer to the HW structure
1049 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1051 struct e1000_phy_info *phy = &hw->phy;
1058 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1066 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1078 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1108 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1113 ret_val = hw->phy.ops.commit(hw);
1120 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1127 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1132 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1137 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1142 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1146 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1148 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1150 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1159 if (!(hw->mac.ops.check_mng_mode(hw))) {
1162 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1167 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1173 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1183 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1188 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1198 * @hw: pointer to the HW structure
1203 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1211 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1214 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1221 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1225 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1230 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1234 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1239 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1244 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1248 ret_val = e1000_setup_copper_link_generic(hw);
1256 * @hw: pointer to the HW structure
1262 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1270 if (hw->phy.media_type == e1000_media_type_copper) {
1271 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1277 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1279 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1288 * @hw: pointer to the HW structure
1294 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1304 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1311 tipg = E1000_READ_REG(hw, E1000_TIPG);
1314 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1317 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1322 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1334 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1343 * @hw: pointer to the HW structure
1348 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1358 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1364 tipg = E1000_READ_REG(hw, E1000_TIPG);
1367 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1370 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1375 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1383 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1392 * @hw: pointer to the HW structure
1400 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1408 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1414 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1415 E1000_WRITE_FLUSH(hw);
1419 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1422 e1000_release_mac_csr_80003es2lan(hw);
1430 * @hw: pointer to the HW structure
1438 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1446 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1452 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1453 E1000_WRITE_FLUSH(hw);
1457 e1000_release_mac_csr_80003es2lan(hw);
1465 * @hw: pointer to the HW structure
1467 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1478 ret_val = e1000_check_alt_mac_addr_generic(hw);
1482 ret_val = e1000_read_mac_addr_generic(hw);
1490 * @hw: pointer to the HW structure
1495 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1498 if (!(hw->mac.ops.check_mng_mode(hw) ||
1499 hw->phy.ops.check_reset_block(hw)))
1500 e1000_power_down_phy_copper(hw);
1507 * @hw: pointer to the HW structure
1511 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1515 e1000_clear_hw_cntrs_base_generic(hw);
1517 E1000_READ_REG(hw, E1000_PRC64);
1518 E1000_READ_REG(hw, E1000_PRC127);
1519 E1000_READ_REG(hw, E1000_PRC255);
1520 E1000_READ_REG(hw, E1000_PRC511);
1521 E1000_READ_REG(hw, E1000_PRC1023);
1522 E1000_READ_REG(hw, E1000_PRC1522);
1523 E1000_READ_REG(hw, E1000_PTC64);
1524 E1000_READ_REG(hw, E1000_PTC127);
1525 E1000_READ_REG(hw, E1000_PTC255);
1526 E1000_READ_REG(hw, E1000_PTC511);
1527 E1000_READ_REG(hw, E1000_PTC1023);
1528 E1000_READ_REG(hw, E1000_PTC1522);
1530 E1000_READ_REG(hw, E1000_ALGNERRC);
1531 E1000_READ_REG(hw, E1000_RXERRC);
1532 E1000_READ_REG(hw, E1000_TNCRS);
1533 E1000_READ_REG(hw, E1000_CEXTERR);
1534 E1000_READ_REG(hw, E1000_TSCTC);
1535 E1000_READ_REG(hw, E1000_TSCTFC);
1537 E1000_READ_REG(hw, E1000_MGTPRC);
1538 E1000_READ_REG(hw, E1000_MGTPDC);
1539 E1000_READ_REG(hw, E1000_MGTPTC);
1541 E1000_READ_REG(hw, E1000_IAC);
1542 E1000_READ_REG(hw, E1000_ICRXOC);
1544 E1000_READ_REG(hw, E1000_ICRXPTC);
1545 E1000_READ_REG(hw, E1000_ICRXATC);
1546 E1000_READ_REG(hw, E1000_ICTXPTC);
1547 E1000_READ_REG(hw, E1000_ICTXATC);
1548 E1000_READ_REG(hw, E1000_ICTXQEC);
1549 E1000_READ_REG(hw, E1000_ICTXQMTC);
1550 E1000_READ_REG(hw, E1000_ICRXDMTC);