contrib/octeon-sdk/cvmx-uctlx-defs.h

56 static inline uint64_t CVMX_UCTLX_BIST_STATUS(unsigned long block_id)
59 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
60 		cvmx_warn("CVMX_UCTLX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
64 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
67 static inline uint64_t CVMX_UCTLX_CLK_RST_CTL(unsigned long block_id)
70 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
71 		cvmx_warn("CVMX_UCTLX_CLK_RST_CTL(%lu) is invalid on this chip\n", block_id);
75 #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
78 static inline uint64_t CVMX_UCTLX_EHCI_CTL(unsigned long block_id)
81 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
82 		cvmx_warn("CVMX_UCTLX_EHCI_CTL(%lu) is invalid on this chip\n", block_id);
86 #define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
89 static inline uint64_t CVMX_UCTLX_EHCI_FLA(unsigned long block_id)
92 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
93 		cvmx_warn("CVMX_UCTLX_EHCI_FLA(%lu) is invalid on this chip\n", block_id);
97 #define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
100 static inline uint64_t CVMX_UCTLX_ERTO_CTL(unsigned long block_id)
103 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
104 		cvmx_warn("CVMX_UCTLX_ERTO_CTL(%lu) is invalid on this chip\n", block_id);
108 #define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
111 static inline uint64_t CVMX_UCTLX_IF_ENA(unsigned long block_id)
114 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
115 		cvmx_warn("CVMX_UCTLX_IF_ENA(%lu) is invalid on this chip\n", block_id);
119 #define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
122 static inline uint64_t CVMX_UCTLX_INT_ENA(unsigned long block_id)
125 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
126 		cvmx_warn("CVMX_UCTLX_INT_ENA(%lu) is invalid on this chip\n", block_id);
130 #define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
133 static inline uint64_t CVMX_UCTLX_INT_REG(unsigned long block_id)
136 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
137 		cvmx_warn("CVMX_UCTLX_INT_REG(%lu) is invalid on this chip\n", block_id);
141 #define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
144 static inline uint64_t CVMX_UCTLX_OHCI_CTL(unsigned long block_id)
147 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
148 		cvmx_warn("CVMX_UCTLX_OHCI_CTL(%lu) is invalid on this chip\n", block_id);
152 #define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
155 static inline uint64_t CVMX_UCTLX_ORTO_CTL(unsigned long block_id)
158 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
159 		cvmx_warn("CVMX_UCTLX_ORTO_CTL(%lu) is invalid on this chip\n", block_id);
163 #define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
166 static inline uint64_t CVMX_UCTLX_PPAF_WM(unsigned long block_id)
169 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
170 		cvmx_warn("CVMX_UCTLX_PPAF_WM(%lu) is invalid on this chip\n", block_id);
174 #define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
177 static inline uint64_t CVMX_UCTLX_UPHY_CTL_STATUS(unsigned long block_id)
180 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
181 		cvmx_warn("CVMX_UCTLX_UPHY_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
185 #define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
188 static inline uint64_t CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(unsigned long offset, unsigned long block_id)
191 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0))))))
192 		cvmx_warn("CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(%lu,%lu) is invalid on this chip\n", offset, block_id);
193 	return CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8;
196 #define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)