Lines Matching refs:block_id
56 static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
60 cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id);
64 #define CVMX_SRIOMAINTX_ASMBLY_ID(block_id) (0x0000000000000008ull)
67 static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id)
70 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
71 cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id);
75 #define CVMX_SRIOMAINTX_ASMBLY_INFO(block_id) (0x000000000000000Cull)
78 static inline uint64_t CVMX_SRIOMAINTX_BAR1_IDXX(unsigned long offset, unsigned long block_id)
81 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1))))))
82 cvmx_warn("CVMX_SRIOMAINTX_BAR1_IDXX(%lu,%lu) is invalid on this chip\n", offset, block_id);
83 return CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4;
86 #define CVMX_SRIOMAINTX_BAR1_IDXX(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4)
89 static inline uint64_t CVMX_SRIOMAINTX_BELL_STATUS(unsigned long block_id)
92 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
93 cvmx_warn("CVMX_SRIOMAINTX_BELL_STATUS(%lu) is invalid on this chip\n", block_id);
97 #define CVMX_SRIOMAINTX_BELL_STATUS(block_id) (0x0000000000200080ull)
100 static inline uint64_t CVMX_SRIOMAINTX_COMP_TAG(unsigned long block_id)
103 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
104 cvmx_warn("CVMX_SRIOMAINTX_COMP_TAG(%lu) is invalid on this chip\n", block_id);
108 #define CVMX_SRIOMAINTX_COMP_TAG(block_id) (0x000000000000006Cull)
111 static inline uint64_t CVMX_SRIOMAINTX_CORE_ENABLES(unsigned long block_id)
114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
115 cvmx_warn("CVMX_SRIOMAINTX_CORE_ENABLES(%lu) is invalid on this chip\n", block_id);
119 #define CVMX_SRIOMAINTX_CORE_ENABLES(block_id) (0x0000000000200070ull)
122 static inline uint64_t CVMX_SRIOMAINTX_DEV_ID(unsigned long block_id)
125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
126 cvmx_warn("CVMX_SRIOMAINTX_DEV_ID(%lu) is invalid on this chip\n", block_id);
130 #define CVMX_SRIOMAINTX_DEV_ID(block_id) (0x0000000000000000ull)
133 static inline uint64_t CVMX_SRIOMAINTX_DEV_REV(unsigned long block_id)
136 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
137 cvmx_warn("CVMX_SRIOMAINTX_DEV_REV(%lu) is invalid on this chip\n", block_id);
141 #define CVMX_SRIOMAINTX_DEV_REV(block_id) (0x0000000000000004ull)
144 static inline uint64_t CVMX_SRIOMAINTX_DST_OPS(unsigned long block_id)
147 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
148 cvmx_warn("CVMX_SRIOMAINTX_DST_OPS(%lu) is invalid on this chip\n", block_id);
152 #define CVMX_SRIOMAINTX_DST_OPS(block_id) (0x000000000000001Cull)
155 static inline uint64_t CVMX_SRIOMAINTX_ERB_ATTR_CAPT(unsigned long block_id)
158 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
159 cvmx_warn("CVMX_SRIOMAINTX_ERB_ATTR_CAPT(%lu) is invalid on this chip\n", block_id);
163 #define CVMX_SRIOMAINTX_ERB_ATTR_CAPT(block_id) (0x0000000000002048ull)
166 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_DET(unsigned long block_id)
169 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
170 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_DET(%lu) is invalid on this chip\n", block_id);
174 #define CVMX_SRIOMAINTX_ERB_ERR_DET(block_id) (0x0000000000002040ull)
177 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE(unsigned long block_id)
180 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
181 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE(%lu) is invalid on this chip\n", block_id);
185 #define CVMX_SRIOMAINTX_ERB_ERR_RATE(block_id) (0x0000000000002068ull)
188 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(unsigned long block_id)
191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
192 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(%lu) is invalid on this chip\n", block_id);
196 #define CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(block_id) (0x0000000000002044ull)
199 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(unsigned long block_id)
202 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
203 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(%lu) is invalid on this chip\n", block_id);
207 #define CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(block_id) (0x000000000000206Cull)
210 static inline uint64_t CVMX_SRIOMAINTX_ERB_HDR(unsigned long block_id)
213 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
214 cvmx_warn("CVMX_SRIOMAINTX_ERB_HDR(%lu) is invalid on this chip\n", block_id);
218 #define CVMX_SRIOMAINTX_ERB_HDR(block_id) (0x0000000000002000ull)
221 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(unsigned long block_id)
224 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
225 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(%lu) is invalid on this chip\n", block_id);
229 #define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(block_id) (0x0000000000002010ull)
232 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(unsigned long block_id)
235 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
236 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(%lu) is invalid on this chip\n", block_id);
240 #define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(block_id) (0x0000000000002014ull)
243 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(unsigned long block_id)
246 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
247 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(%lu) is invalid on this chip\n", block_id);
251 #define CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(block_id) (0x000000000000201Cull)
254 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID(unsigned long block_id)
257 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
258 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID(%lu) is invalid on this chip\n", block_id);
262 #define CVMX_SRIOMAINTX_ERB_LT_DEV_ID(block_id) (0x0000000000002028ull)
265 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(unsigned long block_id)
268 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
269 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(%lu) is invalid on this chip\n", block_id);
273 #define CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(block_id) (0x0000000000002018ull)
276 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_DET(unsigned long block_id)
279 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
280 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_DET(%lu) is invalid on this chip\n", block_id);
284 #define CVMX_SRIOMAINTX_ERB_LT_ERR_DET(block_id) (0x0000000000002008ull)
287 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_EN(unsigned long block_id)
290 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
291 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_EN(%lu) is invalid on this chip\n", block_id);
295 #define CVMX_SRIOMAINTX_ERB_LT_ERR_EN(block_id) (0x000000000000200Cull)
298 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(unsigned long block_id)
301 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
302 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(%lu) is invalid on this chip\n", block_id);
306 #define CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(block_id) (0x0000000000002050ull)
309 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(unsigned long block_id)
312 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
313 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(%lu) is invalid on this chip\n", block_id);
317 #define CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(block_id) (0x0000000000002054ull)
320 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(unsigned long block_id)
323 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
324 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(%lu) is invalid on this chip\n", block_id);
328 #define CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(block_id) (0x0000000000002058ull)
331 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(unsigned long block_id)
334 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
335 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(%lu) is invalid on this chip\n", block_id);
339 #define CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(block_id) (0x000000000000204Cull)
342 static inline uint64_t CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(unsigned long block_id)
345 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
346 cvmx_warn("CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(%lu) is invalid on this chip\n", block_id);
350 #define CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(block_id) (0x0000000000000068ull)
353 static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(unsigned long block_id)
356 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
357 cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(%lu) is invalid on this chip\n", block_id);
361 #define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(block_id) (0x0000000000102000ull)
364 static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(unsigned long block_id)
367 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
368 cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(%lu) is invalid on this chip\n", block_id);
372 #define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(block_id) (0x0000000000102004ull)
375 static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(unsigned long block_id)
378 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
379 cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(%lu) is invalid on this chip\n", block_id);
383 #define CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(block_id) (0x0000000000107028ull)
386 static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_STAT(unsigned long block_id)
389 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
390 cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_STAT(%lu) is invalid on this chip\n", block_id);
394 #define CVMX_SRIOMAINTX_IR_PD_PHY_STAT(block_id) (0x000000000010702Cull)
397 static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(unsigned long block_id)
400 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
401 cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(%lu) is invalid on this chip\n", block_id);
405 #define CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(block_id) (0x0000000000107020ull)
408 static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_STAT(unsigned long block_id)
411 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
412 cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_STAT(%lu) is invalid on this chip\n", block_id);
416 #define CVMX_SRIOMAINTX_IR_PI_PHY_STAT(block_id) (0x0000000000107024ull)
419 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_CTRL(unsigned long block_id)
422 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
423 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_CTRL(%lu) is invalid on this chip\n", block_id);
427 #define CVMX_SRIOMAINTX_IR_SP_RX_CTRL(block_id) (0x000000000010700Cull)
430 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_DATA(unsigned long block_id)
433 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
434 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_DATA(%lu) is invalid on this chip\n", block_id);
438 #define CVMX_SRIOMAINTX_IR_SP_RX_DATA(block_id) (0x0000000000107014ull)
441 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_STAT(unsigned long block_id)
444 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
445 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_STAT(%lu) is invalid on this chip\n", block_id);
449 #define CVMX_SRIOMAINTX_IR_SP_RX_STAT(block_id) (0x0000000000107010ull)
452 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_CTRL(unsigned long block_id)
455 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
456 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_CTRL(%lu) is invalid on this chip\n", block_id);
460 #define CVMX_SRIOMAINTX_IR_SP_TX_CTRL(block_id) (0x0000000000107000ull)
463 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_DATA(unsigned long block_id)
466 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
467 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_DATA(%lu) is invalid on this chip\n", block_id);
471 #define CVMX_SRIOMAINTX_IR_SP_TX_DATA(block_id) (0x0000000000107008ull)
474 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_STAT(unsigned long block_id)
477 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
478 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_STAT(%lu) is invalid on this chip\n", block_id);
482 #define CVMX_SRIOMAINTX_IR_SP_TX_STAT(block_id) (0x0000000000107004ull)
485 static inline uint64_t CVMX_SRIOMAINTX_LANE_X_STATUS_0(unsigned long offset, unsigned long block_id)
488 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
489 cvmx_warn("CVMX_SRIOMAINTX_LANE_X_STATUS_0(%lu,%lu) is invalid on this chip\n", offset, block_id);
490 return CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32;
493 #define CVMX_SRIOMAINTX_LANE_X_STATUS_0(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32)
496 static inline uint64_t CVMX_SRIOMAINTX_LCS_BA0(unsigned long block_id)
499 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
500 cvmx_warn("CVMX_SRIOMAINTX_LCS_BA0(%lu) is invalid on this chip\n", block_id);
504 #define CVMX_SRIOMAINTX_LCS_BA0(block_id) (0x0000000000000058ull)
507 static inline uint64_t CVMX_SRIOMAINTX_LCS_BA1(unsigned long block_id)
510 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
511 cvmx_warn("CVMX_SRIOMAINTX_LCS_BA1(%lu) is invalid on this chip\n", block_id);
515 #define CVMX_SRIOMAINTX_LCS_BA1(block_id) (0x000000000000005Cull)
518 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START0(unsigned long block_id)
521 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
522 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START0(%lu) is invalid on this chip\n", block_id);
526 #define CVMX_SRIOMAINTX_M2S_BAR0_START0(block_id) (0x0000000000200000ull)
529 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START1(unsigned long block_id)
532 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
533 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START1(%lu) is invalid on this chip\n", block_id);
537 #define CVMX_SRIOMAINTX_M2S_BAR0_START1(block_id) (0x0000000000200004ull)
540 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START0(unsigned long block_id)
543 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
544 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START0(%lu) is invalid on this chip\n", block_id);
548 #define CVMX_SRIOMAINTX_M2S_BAR1_START0(block_id) (0x0000000000200008ull)
551 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START1(unsigned long block_id)
554 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
555 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START1(%lu) is invalid on this chip\n", block_id);
559 #define CVMX_SRIOMAINTX_M2S_BAR1_START1(block_id) (0x000000000020000Cull)
562 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR2_START(unsigned long block_id)
565 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
566 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR2_START(%lu) is invalid on this chip\n", block_id);
570 #define CVMX_SRIOMAINTX_M2S_BAR2_START(block_id) (0x0000000000200050ull)
573 static inline uint64_t CVMX_SRIOMAINTX_MAC_CTRL(unsigned long block_id)
576 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
577 cvmx_warn("CVMX_SRIOMAINTX_MAC_CTRL(%lu) is invalid on this chip\n", block_id);
581 #define CVMX_SRIOMAINTX_MAC_CTRL(block_id) (0x0000000000200068ull)
584 static inline uint64_t CVMX_SRIOMAINTX_PE_FEAT(unsigned long block_id)
587 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
588 cvmx_warn("CVMX_SRIOMAINTX_PE_FEAT(%lu) is invalid on this chip\n", block_id);
592 #define CVMX_SRIOMAINTX_PE_FEAT(block_id) (0x0000000000000010ull)
595 static inline uint64_t CVMX_SRIOMAINTX_PE_LLC(unsigned long block_id)
598 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
599 cvmx_warn("CVMX_SRIOMAINTX_PE_LLC(%lu) is invalid on this chip\n", block_id);
603 #define CVMX_SRIOMAINTX_PE_LLC(block_id) (0x000000000000004Cull)
606 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL(unsigned long block_id)
609 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
610 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL(%lu) is invalid on this chip\n", block_id);
614 #define CVMX_SRIOMAINTX_PORT_0_CTL(block_id) (0x000000000000015Cull)
617 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long block_id)
620 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
621 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL2(%lu) is invalid on this chip\n", block_id);
625 #define CVMX_SRIOMAINTX_PORT_0_CTL2(block_id) (0x0000000000000154ull)
628 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_ERR_STAT(unsigned long block_id)
631 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
632 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_ERR_STAT(%lu) is invalid on this chip\n", block_id);
636 #define CVMX_SRIOMAINTX_PORT_0_ERR_STAT(block_id) (0x0000000000000158ull)
639 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_REQ(unsigned long block_id)
642 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
643 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_REQ(%lu) is invalid on this chip\n", block_id);
647 #define CVMX_SRIOMAINTX_PORT_0_LINK_REQ(block_id) (0x0000000000000140ull)
650 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_RESP(unsigned long block_id)
653 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
654 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_RESP(%lu) is invalid on this chip\n", block_id);
658 #define CVMX_SRIOMAINTX_PORT_0_LINK_RESP(block_id) (0x0000000000000144ull)
661 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(unsigned long block_id)
664 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
665 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(%lu) is invalid on this chip\n", block_id);
669 #define CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(block_id) (0x0000000000000148ull)
672 static inline uint64_t CVMX_SRIOMAINTX_PORT_GEN_CTL(unsigned long block_id)
675 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
676 cvmx_warn("CVMX_SRIOMAINTX_PORT_GEN_CTL(%lu) is invalid on this chip\n", block_id);
680 #define CVMX_SRIOMAINTX_PORT_GEN_CTL(block_id) (0x000000000000013Cull)
683 static inline uint64_t CVMX_SRIOMAINTX_PORT_LT_CTL(unsigned long block_id)
686 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
687 cvmx_warn("CVMX_SRIOMAINTX_PORT_LT_CTL(%lu) is invalid on this chip\n", block_id);
691 #define CVMX_SRIOMAINTX_PORT_LT_CTL(block_id) (0x0000000000000120ull)
694 static inline uint64_t CVMX_SRIOMAINTX_PORT_MBH0(unsigned long block_id)
697 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
698 cvmx_warn("CVMX_SRIOMAINTX_PORT_MBH0(%lu) is invalid on this chip\n", block_id);
702 #define CVMX_SRIOMAINTX_PORT_MBH0(block_id) (0x0000000000000100ull)
705 static inline uint64_t CVMX_SRIOMAINTX_PORT_RT_CTL(unsigned long block_id)
708 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
709 cvmx_warn("CVMX_SRIOMAINTX_PORT_RT_CTL(%lu) is invalid on this chip\n", block_id);
713 #define CVMX_SRIOMAINTX_PORT_RT_CTL(block_id) (0x0000000000000124ull)
716 static inline uint64_t CVMX_SRIOMAINTX_PORT_TTL_CTL(unsigned long block_id)
719 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
720 cvmx_warn("CVMX_SRIOMAINTX_PORT_TTL_CTL(%lu) is invalid on this chip\n", block_id);
724 #define CVMX_SRIOMAINTX_PORT_TTL_CTL(block_id) (0x000000000000012Cull)
727 static inline uint64_t CVMX_SRIOMAINTX_PRI_DEV_ID(unsigned long block_id)
730 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
731 cvmx_warn("CVMX_SRIOMAINTX_PRI_DEV_ID(%lu) is invalid on this chip\n", block_id);
735 #define CVMX_SRIOMAINTX_PRI_DEV_ID(block_id) (0x0000000000000060ull)
738 static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_CTRL(unsigned long block_id)
741 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
742 cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_CTRL(%lu) is invalid on this chip\n", block_id);
746 #define CVMX_SRIOMAINTX_SEC_DEV_CTRL(block_id) (0x0000000000200064ull)
749 static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_ID(unsigned long block_id)
752 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
753 cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_ID(%lu) is invalid on this chip\n", block_id);
757 #define CVMX_SRIOMAINTX_SEC_DEV_ID(block_id) (0x0000000000200060ull)
760 static inline uint64_t CVMX_SRIOMAINTX_SERIAL_LANE_HDR(unsigned long block_id)
763 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
764 cvmx_warn("CVMX_SRIOMAINTX_SERIAL_LANE_HDR(%lu) is invalid on this chip\n", block_id);
768 #define CVMX_SRIOMAINTX_SERIAL_LANE_HDR(block_id) (0x0000000000001000ull)
771 static inline uint64_t CVMX_SRIOMAINTX_SRC_OPS(unsigned long block_id)
774 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
775 cvmx_warn("CVMX_SRIOMAINTX_SRC_OPS(%lu) is invalid on this chip\n", block_id);
779 #define CVMX_SRIOMAINTX_SRC_OPS(block_id) (0x0000000000000018ull)
782 static inline uint64_t CVMX_SRIOMAINTX_TX_DROP(unsigned long block_id)
785 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
786 cvmx_warn("CVMX_SRIOMAINTX_TX_DROP(%lu) is invalid on this chip\n", block_id);
790 #define CVMX_SRIOMAINTX_TX_DROP(block_id) (0x000000000020006Cull)