Lines Matching refs:tim
599 uint64_t tim : 1; /**< TIM interrupt
633 uint64_t tim : 1;
1505 uint64_t tim : 1; /**< TIM interrupt enable */
1535 uint64_t tim : 1;
1662 uint64_t tim : 1; /**< TIM interrupt enable */
1690 uint64_t tim : 1;
1748 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
1780 uint64_t tim : 1;
1864 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
1894 uint64_t tim : 1;
1952 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
1984 uint64_t tim : 1;
2068 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
2098 uint64_t tim : 1;
2712 uint64_t tim : 1; /**< TIM interrupt enable */
2742 uint64_t tim : 1;
2856 uint64_t tim : 1; /**< TIM interrupt enable */
2884 uint64_t tim : 1;
2942 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
2974 uint64_t tim : 1;
3058 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
3088 uint64_t tim : 1;
3146 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
3178 uint64_t tim : 1;
3262 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
3292 uint64_t tim : 1;
4217 uint64_t tim : 1; /**< TIM interrupt
4259 uint64_t tim : 1;
4403 uint64_t tim : 1; /**< TIM interrupt
4443 uint64_t tim : 1;