Lines Matching refs:mbox
889 uint64_t mbox : 2; /**< Two mailbox/PCIe/sRIO interrupt enables */
895 uint64_t mbox : 2;
936 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
942 uint64_t mbox : 2;
980 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
986 uint64_t mbox : 2;
1020 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
1026 uint64_t mbox : 2;
1065 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
1071 uint64_t mbox : 2;
1115 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
1121 uint64_t mbox : 2;
1185 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe/sRIO interrupt
1192 uint64_t mbox : 2;
1235 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
1241 uint64_t mbox : 2;
1279 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
1285 uint64_t mbox : 2;
1340 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe/sRIO interrupt
1347 uint64_t mbox : 2;
1390 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
1396 uint64_t mbox : 2;
1434 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
1440 uint64_t mbox : 2;
2158 uint64_t mbox : 2; /**< Two mailbox interrupt enables */
2164 uint64_t mbox : 2;
2205 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2211 uint64_t mbox : 2;
2252 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2258 uint64_t mbox : 2;
2302 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2308 uint64_t mbox : 2;
2345 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2351 uint64_t mbox : 2;
2407 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
2413 uint64_t mbox : 2;
2456 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2462 uint64_t mbox : 2;
2500 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2506 uint64_t mbox : 2;
2561 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
2567 uint64_t mbox : 2;
2610 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2616 uint64_t mbox : 2;
2654 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2660 uint64_t mbox : 2;
3377 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
3389 uint64_t mbox : 2;
3438 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
3449 uint64_t mbox : 2;
3495 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
3506 uint64_t mbox : 2;
3550 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
3561 uint64_t mbox : 2;
3616 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-7
3627 uint64_t mbox : 2;
3681 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-23
3692 uint64_t mbox : 2;
3777 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5
3787 uint64_t mbox : 2;
3833 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
3844 uint64_t mbox : 2;
3898 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-3
3907 uint64_t mbox : 2;
3958 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
3967 uint64_t mbox : 2;
4011 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
4022 uint64_t mbox : 2;
4100 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */
4108 uint64_t mbox : 2;