Lines Matching defs:dmae
1508 struct dmae_cmd *dmae,
1516 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i));
1572 struct dmae_cmd *dmae,
1576 memset(dmae, 0, sizeof(struct dmae_cmd));
1579 dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type,
1583 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
1584 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
1585 dmae->comp_val = DMAE_COMP_VAL;
1591 struct dmae_cmd *dmae)
1602 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
1637 struct dmae_cmd dmae;
1656 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
1659 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
1660 dmae.src_addr_hi = 0;
1661 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
1662 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
1663 dmae.len = len32;
1666 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1677 struct dmae_cmd dmae;
1693 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
1696 dmae.src_addr_lo = U64_LO(dma_addr);
1697 dmae.src_addr_hi = U64_HI(dma_addr);
1698 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
1699 dmae.dst_addr_hi = 0;
1700 dmae.len = len32;
1703 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
10986 * respond. The write queue in PGLUE would stuck, dmae commands
15489 * use rd/wr since we cannot use dmae. This is safe
17155 * dmae-operations (writing to pram for example.)
17545 * common phase, we need to enable it here before any dmae access are