Lines Matching refs:Record
32 #include "llvm/TableGen/Record.h"
53 CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
80 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
92 std::vector<Record*> Parts =
99 for (Record *Part : Parts)
156 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
169 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
170 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
191 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases");
192 for (Record *Alias : Aliases) {
613 std::vector<std::unique_ptr<Record>> &SynthDefs;
615 TupleExpander(std::vector<std::unique_ptr<Record>> &SynthDefs)
618 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override {
619 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
640 Record *RegisterCl = Def->getRecords().getClass("Register");
648 Record *Proto = Lists[0][n];
652 Record *Reg = Lists[i][n];
669 // Create a new Record representing the synthesized register. This record
673 std::make_unique<Record>(Name, Def->getLoc(), Def->getRecords()));
674 Record *NewReg = SynthDefs.back().get();
678 ArrayRef<std::pair<Record *, SMRange>> Supers = Proto->getSuperClasses();
741 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
745 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
747 Record *Type = TypeList[i];
1115 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
1124 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
1131 std::vector<Record*> Tups =
1134 for (Record *R : Tups) {
1135 std::vector<Record *> TupRegs = *Sets.expand(R);
1137 for (Record *RC : TupRegs)
1197 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
1220 // Create a synthetic CodeGenSubRegIndex without a corresponding Record.
1227 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
1237 CodeGenRegBank::findSubRegIdx(const Record* Def) const {
1242 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
1252 if (Record *Def = RC->getDef())
1278 CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const {
2348 CodeGenRegBank::getRegClassForRegister(Record *R) {
2388 CodeGenRegBank::getMinimalPhysRegClass(Record *RegRecord,
2402 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {