Lines Matching defs:Reg1
415 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
927 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
928 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
956 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
957 // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
967 if (parseRegister(Reg1))
986 if (parseIntegerRegister(Reg1, RegGroup))
1040 Register Reg1, Reg2;
1047 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1060 // If we have Reg1, it must be an address register.
1062 if (parseAddressRegister(Reg1))
1064 Base = Regs[Reg1.Num];
1073 // If we have Reg1, it must be an address register.
1075 if (parseAddressRegister(Reg1))
1080 Index = Regs[Reg1.Num];
1082 Base = Regs[Reg1.Num];
1110 // We must have Reg1, and it must be a GPR.
1111 if (!HaveReg1 || Reg1.Group != RegGR) {
1115 LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1124 // We must have Reg1, and it must be a vector register.
1125 if (!HaveReg1 || Reg1.Group != RegV) {
1129 Index = SystemZMC::VR128Regs[Reg1.Num];
1365 Register Reg1, Reg2;
1369 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1374 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1375 && parseAddressRegister(Reg1))