Lines Matching refs:NVPTXTargetLowering
90 int NVPTXTargetLowering::getDivF32Level() const {
103 bool NVPTXTargetLowering::usePrecSqrtF32() const {
113 bool NVPTXTargetLowering::useF32FTZ(const MachineFunction &MF) const {
326 // NVPTXTargetLowering Constructor.
327 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
575 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
1176 NVPTXTargetLowering::getPreferredVectorAction(MVT VT) const {
1184 SDValue NVPTXTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
1234 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
1242 std::string NVPTXTargetLowering::getPrototype(
1354 Align NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1404 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1626 // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
1872 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1900 SDValue NVPTXTargetLowering::LowerBUILD_VECTOR(SDValue Op,
1917 SDValue NVPTXTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
1944 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
2005 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
2060 SDValue NVPTXTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2079 SDValue NVPTXTargetLowering::LowerFROUND32(SDValue Op,
2120 SDValue NVPTXTargetLowering::LowerFROUND64(SDValue Op,
2155 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2191 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
2207 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2231 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
2249 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2270 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
2393 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
2409 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
2445 SDValue NVPTXTargetLowering::LowerFormalArguments(
2643 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2726 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
3436 bool NVPTXTargetLowering::getTgtMemIntrinsic(
4196 bool NVPTXTargetLowering::isLegalAddressingMode(const DataLayout &DL,
4233 NVPTXTargetLowering::ConstraintType
4234 NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
4255 NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
4284 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
4301 bool NVPTXTargetLowering::allowUnsafeFPMath(MachineFunction &MF) const {
4350 const auto *TLI = static_cast<const NVPTXTargetLowering *>(
4735 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
5026 void NVPTXTargetLowering::ReplaceNodeResults(