Lines Matching refs:RegB
131 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
135 unsigned RegA, unsigned RegB, unsigned Dist);
423 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
424 if (RegA == RegB)
426 if (!RegA || !RegB)
428 return TRI->regsOverlap(RegA, RegB);
489 // -RegB is not tied to a register and RegC is compatible with RegA.
490 // -RegB is tied to the wrong physical register, but RegC is.
491 // -RegB is tied to the wrong physical register, and RegC isn't tied.
495 // -RegC is not tied to a register and RegB is compatible with RegA.
496 // -RegC is tied to the wrong physical register, but RegB is.
497 // -RegC is tied to the wrong physical register, and RegB isn't tied.
574 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
581 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
593 unsigned RegA, unsigned RegB,
617 DstRegMap.erase(RegB);
1363 unsigned RegB = 0;
1372 // Grab RegB from the instruction because it may have changed if the
1374 RegB = MI->getOperand(SrcIdx).getReg();
1377 if (RegA == RegB) {
1386 assert(Register::isVirtualRegister(RegB) &&
1404 MIB.addReg(RegB, 0, SubRegB);
1405 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1414 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1440 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1448 if (Register::isVirtualRegister(RegA) && Register::isVirtualRegister(RegB))
1457 SrcRegMap[RegA] = RegB;
1465 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1482 LV && LV->getVarInfo(RegB).removeKill(*MI)) {
1485 LV->addVirtualRegisterKilled(RegB, *PrevMI);
1490 LiveInterval &LI = LIS->getInterval(RegB);
1493 assert(I != LI.end() && "RegB must be live-in to use.");
1505 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {