Lines Matching refs:v2i64
221 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
222 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
369 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 10 },
370 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 2 },
373 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 10 },
374 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2 },
375 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 8 },
376 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 2 },
583 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
605 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
628 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
704 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
705 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
706 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
707 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
732 // the vectorized code. Because we have support for v2i64 but not i64 those
734 // To work around this we increase the cost of v2i64 operations to make them
736 if (LT.second == MVT::v2i64 &&