Lines Matching defs:tmpl
8370 struct rsrc tmpl;
8378 tmpl.dependency = dep;
8379 tmpl.note = note;
8380 tmpl.insn_srlz = tmpl.data_srlz = 0;
8381 tmpl.qp_regno = CURR_SLOT.qp_regno;
8382 tmpl.link_to_qp_branch = 1;
8383 tmpl.mem_offset.hint = 0;
8384 tmpl.mem_offset.offset = 0;
8385 tmpl.mem_offset.base = 0;
8386 tmpl.specific = 1;
8387 tmpl.index = -1;
8388 tmpl.cmp_type = CMP_NONE;
8389 tmpl.depind = 0;
8390 tmpl.file = NULL;
8391 tmpl.line = 0;
8392 tmpl.path = 0;
8413 specs[count] = tmpl;
8422 specs[count] = tmpl;
8439 specs[count++] = tmpl;
8451 specs[count] = tmpl;
8482 specs[count] = tmpl;
8502 specs[count] = tmpl;
8511 specs[count] = tmpl;
8516 specs[count] = tmpl;
8539 specs[count] = tmpl;
8550 specs[count] = tmpl;
8567 specs[count] = tmpl;
8572 specs[count] = tmpl;
8592 specs[count] = tmpl;
8597 specs[count] = tmpl;
8604 specs[count] = tmpl;
8622 specs[count] = tmpl;
8627 specs[count] = tmpl;
8643 specs[count] = tmpl;
8663 specs[count] = tmpl;
8672 specs[count] = tmpl;
8679 specs[count] = tmpl;
8687 specs[count] = tmpl;
8705 specs[count] = tmpl;
8710 specs[count] = tmpl;
8730 specs[count] = tmpl;
8735 specs[count] = tmpl;
8755 specs[count] = tmpl;
8760 specs[count] = tmpl;
8767 specs[count] = tmpl;
8787 specs[count] = tmpl;
8799 specs[count] = tmpl;
8820 specs[count] = tmpl;
8831 specs[count] = tmpl;
8853 specs[count] = tmpl;
8865 specs[count] = tmpl;
8878 specs[count] = tmpl;
8890 specs[count] = tmpl;
8898 specs[count] = tmpl;
8924 specs[count] = tmpl;
8944 specs[count] = tmpl;
8958 specs[count] = tmpl;
8979 specs[count] = tmpl;
8994 specs[count] = tmpl;
9011 specs[count] = tmpl;
9020 specs[count] = tmpl;
9030 specs[count] = tmpl;
9037 specs[count] = tmpl;
9056 specs[count] = tmpl;
9071 specs[count] = tmpl;
9080 specs[count] = tmpl;
9101 specs[count] = tmpl;
9116 specs[count] = tmpl;
9133 specs[count] = tmpl;
9142 specs[count] = tmpl;
9152 specs[count] = tmpl;
9159 specs[count] = tmpl;
9180 specs[count++] = tmpl;
9190 specs[count++] = tmpl;
9200 specs[count++] = tmpl;
9209 specs[count++] = tmpl;
9214 specs[count++] = tmpl;
9241 specs[count++] = tmpl;
9250 specs[count++] = tmpl;
9271 specs[count++] = tmpl;
9276 specs[count++] = tmpl;
9296 specs[count++] = tmpl;
9314 specs[count++] = tmpl;
9332 specs[count++] = tmpl;
9348 specs[count++] = tmpl;
9365 specs[count++] = tmpl;
9370 specs[count++] = tmpl;
9382 specs[count++] = tmpl;
9397 specs[count++] = tmpl;
9404 specs[count++] = tmpl;
9420 specs[count++] = tmpl;
9427 specs[count++] = tmpl;
9446 specs[count++] = tmpl;
9457 specs[count++] = tmpl;
9464 specs[count++] = tmpl;
9480 specs[count++] = tmpl;
9487 specs[count++] = tmpl;
9498 specs[count++] = tmpl;
9517 specs[count] = tmpl;
9529 specs[count] = tmpl;
9539 specs[count] = tmpl;
9546 specs[count] = tmpl;
9557 specs[count++] = tmpl;
9565 specs[count++] = tmpl;
9574 specs[count++] = tmpl;
9581 specs[count++] = tmpl;
9597 specs[count] = tmpl;
9605 specs[count] = tmpl;
9614 specs[count++] = tmpl;
9635 specs[count++] = tmpl;
9645 specs[count++] = tmpl;
9654 specs[count++] = tmpl;
9661 specs[count++] = tmpl;
9667 specs[count++] = tmpl;