Lines Matching refs:IsLP64
46 IsLP64 = STI.isTarget64BitLP64();
98 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
99 if (IsLP64) {
110 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
111 if (IsLP64) {
130 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
131 if (IsLP64) {
141 static unsigned getLEArOpcode(unsigned IsLP64) {
142 return IsLP64 ? X86::LEA64r : X86::LEA32r;
1990 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2002 if (IsLP64)
2037 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2075 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2088 TlsOffset = IsLP64 ? 0x70 : 0x40;
2106 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2108 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2111 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2149 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2153 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2191 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2192 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2193 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2194 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2195 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
2372 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);