Lines Matching defs:Reg
31 // Reg should be a 32-bit GPR. Return true if it is a high register rather
33 static bool isHighReg(unsigned int Reg) {
34 if (SystemZ::GRH32BitRegClass.contains(Reg))
36 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
111 unsigned Reg = MI->getOperand(0).getReg();
112 bool IsHigh = isHighReg(Reg);
146 unsigned Reg = MI->getOperand(0).getReg();
147 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
423 // If Reg is a virtual register, return its definition, otherwise return null.
424 static MachineInstr *getDef(unsigned Reg,
426 if (TargetRegisterInfo::isPhysicalRegister(Reg))
428 return MRI->getUniqueVRegDef(Reg);
1279 unsigned Reg, uint64_t Value) const {
1293 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);