Lines Matching refs:Inst
183 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
184 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
248 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
249 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
252 if (RelaxedOp == Inst.getOpcode()) {
255 Inst.dump_pretty(OS);
262 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
273 Res = Inst;
864 const MCCFIInstruction &Inst = Instrs[i];
865 switch (Inst.getOperation()) {
867 CFARegisterOffset = -Inst.getOffset();
868 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
871 CFARegisterOffset = -Inst.getOffset();
874 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
877 Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
879 RegOffsets[Reg] = Inst.getOffset();
881 RegOffsets[Reg] = Inst.getOffset();
886 << Inst.getRegister() << "\n");
898 "unwind encoding, opcode=" << Inst.getOperation()