Lines Matching refs:val
54 #define VXGE_HAL_G3FBCT_CONFIG0_RD_CMD_LATENCY_RPATH(val) vBIT(val, 5, 3)
55 #define VXGE_HAL_G3FBCT_CONFIG0_RD_CMD_LATENCY(val) vBIT(val, 13, 3)
56 #define VXGE_HAL_G3FBCT_CONFIG0_REFRESH_PER(val) vBIT(val, 16, 16)
57 #define VXGE_HAL_G3FBCT_CONFIG0_TRC(val) vBIT(val, 35, 5)
58 #define VXGE_HAL_G3FBCT_CONFIG0_TRRD(val) vBIT(val, 44, 4)
59 #define VXGE_HAL_G3FBCT_CONFIG0_TFAW(val) vBIT(val, 50, 6)
60 #define VXGE_HAL_G3FBCT_CONFIG0_RD_FIFO_THR(val) vBIT(val, 58, 6)
62 #define VXGE_HAL_G3FBCT_CONFIG1_BIC_THR(val) vBIT(val, 3, 5)
65 #define VXGE_HAL_G3FBCT_CONFIG1_RD_SAMPLING(val) vBIT(val, 29, 3)
67 #define VXGE_HAL_G3FBCT_CONFIG1_BIC_HI_THR(val) vBIT(val, 43, 5)
68 #define VXGE_HAL_G3FBCT_CONFIG1_BIC_MODE(val) vBIT(val, 54, 2)
69 #define VXGE_HAL_G3FBCT_CONFIG1_ECC_ENABLE(val) vBIT(val, 57, 7)
71 #define VXGE_HAL_G3FBCT_CONFIG2_DEV_USE_ENABLE(val) vBIT(val, 6, 2)
72 #define VXGE_HAL_G3FBCT_CONFIG2_DEV_USE_VALUE(val) vBIT(val, 9, 7)
73 #define VXGE_HAL_G3FBCT_CONFIG2_ARBITER_CTRL(val) vBIT(val, 22, 2)
76 #define VXGE_HAL_G3FBCT_CONFIG2_LAST_CADD(val) vBIT(val, 43, 13)
78 #define VXGE_HAL_G3FBCT_INIT0_MRS_BAD(val) vBIT(val, 5, 3)
79 #define VXGE_HAL_G3FBCT_INIT0_MRS_WL(val) vBIT(val, 13, 3)
82 #define VXGE_HAL_G3FBCT_INIT0_MRS_CL(val) vBIT(val, 44, 4)
84 #define VXGE_HAL_G3FBCT_INIT0_MRS_BL(val) vBIT(val, 62, 2)
86 #define VXGE_HAL_G3FBCT_INIT1_EMRS_BAD(val) vBIT(val, 5, 3)
91 #define VXGE_HAL_G3FBCT_INIT1_EMRS_TWR(val) vBIT(val, 53, 3)
92 #define VXGE_HAL_G3FBCT_INIT1_EMRS_DQ_TER(val) vBIT(val, 62, 2)
94 #define VXGE_HAL_G3FBCT_INIT2_EMRS_DR_STR(val) vBIT(val, 6, 2)
96 #define VXGE_HAL_G3FBCT_INIT2_POWER_UP_DELAY(val) vBIT(val, 16, 24)
97 #define VXGE_HAL_G3FBCT_INIT2_ACTIVE_CMD_DELAY(val) vBIT(val, 40, 24)
99 #define VXGE_HAL_G3FBCT_INIT3_TRP_DELAY(val) vBIT(val, 0, 8)
100 #define VXGE_HAL_G3FBCT_INIT3_TMRD_DELAY(val) vBIT(val, 8, 8)
101 #define VXGE_HAL_G3FBCT_INIT3_TWR2PRE_DELAY(val) vBIT(val, 16, 8)
102 #define VXGE_HAL_G3FBCT_INIT3_TRD2PRE_DELAY(val) vBIT(val, 24, 8)
103 #define VXGE_HAL_G3FBCT_INIT3_TRCDR_DELAY(val) vBIT(val, 32, 8)
104 #define VXGE_HAL_G3FBCT_INIT3_TRCDW_DELAY(val) vBIT(val, 40, 8)
105 #define VXGE_HAL_G3FBCT_INIT3_TWR2RD_DELAY(val) vBIT(val, 48, 8)
106 #define VXGE_HAL_G3FBCT_INIT3_TRD2WR_DELAY(val) vBIT(val, 56, 8)
108 #define VXGE_HAL_G3FBCT_INIT4_TRFC_DELAY(val) vBIT(val, 0, 8)
109 #define VXGE_HAL_G3FBCT_INIT4_REFRESH_BURSTS(val) vBIT(val, 12, 4)
111 #define VXGE_HAL_G3FBCT_INIT4_VENDOR_ID(val) vBIT(val, 32, 8)
112 #define VXGE_HAL_G3FBCT_INIT4_OOO_DEPTH(val) vBIT(val, 42, 6)
116 #define VXGE_HAL_G3FBCT_INIT5_TRAS_DELAY(val) vBIT(val, 3, 5)
117 #define VXGE_HAL_G3FBCT_INIT5_TVID_DELAY(val) vBIT(val, 8, 8)
118 #define VXGE_HAL_G3FBCT_INIT5_TWR_APRE2CMD(val) vBIT(val, 16, 8)
119 #define VXGE_HAL_G3FBCT_INIT5_TRD_APRE2CMD(val) vBIT(val, 24, 8)
120 #define VXGE_HAL_G3FBCT_INIT5_TWR_APRE2CMD_CON(val) vBIT(val, 32, 8)
121 #define VXGE_HAL_G3FBCT_INIT5_GDDR3_DLL_DELAY(val) vBIT(val, 40, 24)
123 #define VXGE_HAL_G3FBCT_DLL_TRAINING1_DLL_TRA_DATA00(val) vBIT(val, 0, 64)
125 #define VXGE_HAL_G3FBCT_DLL_TRAINING2_DLL_TRA_DATA01(val) vBIT(val, 0, 64)
127 #define VXGE_HAL_G3FBCT_DLL_TRAINING3_DLL_TRA_DATA10(val) vBIT(val, 0, 64)
129 #define VXGE_HAL_G3FBCT_DLL_TRAINING4_DLL_TRA_DATA11(val) vBIT(val, 0, 64)
131 #define VXGE_HAL_G3FBCT_DLL_TRAINING6_DLL_TRA_DATA20(val) vBIT(val, 0, 64)
133 #define VXGE_HAL_G3FBCT_DLL_TRAINING7_DLL_TRA_DATA21(val) vBIT(val, 0, 64)
135 #define VXGE_HAL_G3FBCT_DLL_TRAINING8_DLL_TRA_DATA30(val) vBIT(val, 0, 64)
137 #define VXGE_HAL_G3FBCT_DLL_TRAINING9_DLL_TRA_DATA31(val) vBIT(val, 0, 64)
139 #define VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_RADD(val) vBIT(val, 2, 14)
140 #define VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_CADD0(val) vBIT(val, 21, 11)
141 #define VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_CADD1(val) vBIT(val, 37, 11)
143 #define VXGE_HAL_G3FBCT_DLL_TRAINING10_DLL_TP_READS(val) vBIT(val, 4, 4)
144 #define VXGE_HAL_G3FBCT_DLL_TRAINING10_DLL_SAMPLES(val) vBIT(val, 8, 8)
145 #define VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_LOOPS(val) vBIT(val, 18, 14)
146 #define VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_PASS_CNT(val) vBIT(val, 33, 7)
147 #define VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_STEP(val) vBIT(val, 41, 7)
149 #define VXGE_HAL_G3FBCT_DLL_TRAINING11_ICTRL_DLL_TRA_CNT(val) vBIT(val, 0, 48)
150 #define VXGE_HAL_G3FBCT_DLL_TRAINING11_ICTRL_DLL_TRA_DIS(val) vBIT(val, 54, 2)
152 #define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2RD_DELAY(val) vBIT(val, 4, 4)
153 #define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2WR_DELAY(val) vBIT(val, 12, 4)
154 #define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2PRE_DELAY(val) vBIT(val, 20, 4)
155 #define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2ACT_DELAY(val) vBIT(val, 28, 4)
156 #define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2RD_DELAY(val) vBIT(val, 36, 4)
157 #define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2WR_DELAY(val) vBIT(val, 44, 4)
158 #define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2PRE_DELAY(val) vBIT(val, 52, 4)
159 #define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2ACT_DELAY(val) vBIT(val, 60, 4)
161 #define VXGE_HAL_G3FBCT_TEST0_TEST_START_RADD(val) vBIT(val, 2, 14)
162 #define VXGE_HAL_G3FBCT_TEST0_TEST_END_RADD(val) vBIT(val, 18, 14)
163 #define VXGE_HAL_G3FBCT_TEST0_TEST_START_CADD(val) vBIT(val, 37, 11)
164 #define VXGE_HAL_G3FBCT_TEST0_TEST_END_CADD(val) vBIT(val, 53, 11)
166 #define VXGE_HAL_G3FBCT_TEST01_TEST_BANK(val) vBIT(val, 0, 8)
167 #define VXGE_HAL_G3FBCT_TEST01_TEST_CTRL(val) vBIT(val, 12, 4)
171 #define VXGE_HAL_G3FBCT_TEST01_ECC_DEC_TEST_FAIL_CNTR(val) vBIT(val, 40, 16)
174 #define VXGE_HAL_G3FBCT_TEST1_TX_TEST_DATA(val) vBIT(val, 0, 64)
176 #define VXGE_HAL_G3FBCT_TEST2_TX_TEST_DATA(val) vBIT(val, 0, 64)
178 #define VXGE_HAL_G3FBCT_TEST11_TX_TEST_DATA1(val) vBIT(val, 0, 64)
180 #define VXGE_HAL_G3FBCT_TEST21_TX_TEST_DATA1(val) vBIT(val, 0, 64)
182 #define VXGE_HAL_G3FBCT_TEST3_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64)
184 #define VXGE_HAL_G3FBCT_TEST4_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64)
186 #define VXGE_HAL_G3FBCT_TEST31_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64)
188 #define VXGE_HAL_G3FBCT_TEST41_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64)
190 #define VXGE_HAL_G3FBCT_TEST5_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64)
192 #define VXGE_HAL_G3FBCT_TEST6_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64)
194 #define VXGE_HAL_G3FBCT_TEST51_ECC_DEC_RX_FAILED_TEST_DATA1(val)\
195 vBIT(val, 0, 64)
197 #define VXGE_HAL_G3FBCT_TEST61_ECC_DEC_RX_FAILED_TEST_DATA1(val)\
198 vBIT(val, 0, 64)
200 #define VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_RADD(val) vBIT(val, 0, 14)
201 #define VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_CADD(val) vBIT(val, 19, 11)
202 #define VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_BANK(val) vBIT(val, 32, 8)
204 #define VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_RADD1(val) vBIT(val, 0, 14)
205 #define VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_CADD1(val) vBIT(val, 19, 11)
206 #define VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_BANK1(val) vBIT(val, 32, 8)
210 #define VXGE_HAL_G3FBCT_LOOP_BACK_TDATA(val) vBIT(val, 0, 32)
214 #define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_IDLE_VAL(val) vBIT(val, 56, 8)
216 #define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_START_VAL(val) vBIT(val, 1, 7)
217 #define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_END_VAL(val) vBIT(val, 9, 7)
218 #define VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_IDLE_VAL(val) vBIT(val, 16, 8)
219 #define VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_START_VAL(val) vBIT(val, 25, 7)
220 #define VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_END_VAL(val) vBIT(val, 33, 7)
221 #define VXGE_HAL_G3FBCT_LOOP_BACK1_STEPS(val) vBIT(val, 45, 3)
222 #define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_MIN_FILTER(val) vBIT(val, 49, 7)
223 #define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_MAX_FILTER(val) vBIT(val, 57, 7)
225 #define VXGE_HAL_G3FBCT_LOOP_BACK2_WDLL_MIN_FILTER(val) vBIT(val, 1, 7)
226 #define VXGE_HAL_G3FBCT_LOOP_BACK2_WDLL_MAX_FILTER(val) vBIT(val, 9, 7)
228 #define VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_RDLL_RESULT(val) vBIT(val, 0, 8)
229 #define VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_WDLL_RESULT(val) vBIT(val, 8, 8)
230 #define VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_RDLL_MON_RESULT(val)\
231 vBIT(val, 16, 8)
233 #define VXGE_HAL_G3FBCT_LOOP_BACK4_LBCTRL_IO_PASS_FAILN(val) vBIT(val, 0, 32)
235 #define VXGE_HAL_G3FBCT_LOOP_BACK5_RDLL_START_IO_VAL(val) vBIT(val, 1, 7)
236 #define VXGE_HAL_G3FBCT_LOOP_BACK5_RDLL_END_IO_VAL(val) vBIT(val, 9, 7)
240 #define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MIN_VAL(val) vBIT(val, 1, 7)
241 #define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MAX_VAL(val) vBIT(val, 9, 7)
242 #define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MON_MIN_VAL(val) vBIT(val, 17, 7)
243 #define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MON_MAX_VAL(val) vBIT(val, 25, 7)
245 #define VXGE_HAL_G3FBCT_LOOP_BACK_WDLL_LBCTRL_MIN_VAL(val) vBIT(val, 1, 7)
246 #define VXGE_HAL_G3FBCT_LOOP_BACK_WDLL_LBCTRL_MAX_VAL(val) vBIT(val, 9, 7)
248 #define VXGE_HAL_G3FBCT_TRAN_WRD_CNT_CTRL_PIPE_WR(val) vBIT(val, 0, 32)
249 #define VXGE_HAL_G3FBCT_TRAN_WRD_CNT_CTRL_PIPE_RD(val) vBIT(val, 32, 32)
251 #define VXGE_HAL_G3FBCT_TRAN_AP_CNT_CTRL_PIPE_ACT(val) vBIT(val, 0, 16)
252 #define VXGE_HAL_G3FBCT_TRAN_AP_CNT_CTRL_PIPE_PRE(val) vBIT(val, 16, 16)
257 #define VXGE_HAL_G3FBCT_G3BIST_BTCTRL_STATUS_MAIN(val) vBIT(val, 21, 3)
258 #define VXGE_HAL_G3FBCT_G3BIST_BTCTRL_STATUS_ICTRL(val) vBIT(val, 29, 3)
385 #define VXGE_HAL_RC_CFG_RXD_ERR_MASK(val) vBIT(val, 0, 4)
397 #define VXGE_HAL_RXD_CFG_1BM_QW_SIZE(val) vBIT(val, 5, 3)
398 #define VXGE_HAL_RXD_CFG_1BM_QW2WRITE(val) vBIT(val, 8, 8)
399 #define VXGE_HAL_RXD_CFG_1BM_HCW_QWOFF(val) vBIT(val, 21, 3)
400 #define VXGE_HAL_RXD_CFG_1BM_RTH_VAL_QWOFF(val) vBIT(val, 29, 3)
401 #define VXGE_HAL_RXD_CFG_1BM_RTH_VAL_W0OFF(val) vBIT(val, 38, 2)
402 #define VXGE_HAL_RXD_CFG_1BM_RTH_VAL_W1OFF(val) vBIT(val, 46, 2)
403 #define VXGE_HAL_RXD_CFG_1BM_HEAD_OWN_QWOFF(val) vBIT(val, 53, 3)
404 #define VXGE_HAL_RXD_CFG_1BM_HEAD_OWN_BOFF(val) vBIT(val, 61, 3)
406 #define VXGE_HAL_RXD_CFG1_1BM_BUFF1_SIZE_QWOFF(val) vBIT(val, 5, 3)
407 #define VXGE_HAL_RXD_CFG1_1BM_TRSF_CODE_QWOFF(val) vBIT(val, 45, 3)
408 #define VXGE_HAL_RXD_CFG1_1BM_TRSF_CODE_BOFF(val) vBIT(val, 53, 3)
409 #define VXGE_HAL_RXD_CFG1_1BM_RTH_BUCKET_DATA_QWOF(val) vBIT(val, 61, 3)
411 #define VXGE_HAL_RXD_CFG2_1BM_RTH_BUCKET_DATA_BOFF(val) vBIT(val, 5, 3)
412 #define VXGE_HAL_RXD_CFG2_1BM_BUFF1_SIZE_WOFF(val) vBIT(val, 14, 2)
413 #define VXGE_HAL_RXD_CFG2_1BM_FRM_INFO_QWOFF(val) vBIT(val, 53, 3)
414 #define VXGE_HAL_RXD_CFG2_1BM_FRM_INFO_BOFF(val) vBIT(val, 61, 3)
416 #define VXGE_HAL_RXD_CFG3_1BM_BUFF1_PTR_QWOFF(val) vBIT(val, 5, 3)
417 #define VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_QWOFF(val) vBIT(val, 45, 3)
418 #define VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_BOFF(val) vBIT(val, 53, 3)
419 #define VXGE_HAL_RXD_CFG3_1BM_HEAD_OWN_BIT_IDX(val) vBIT(val, 57, 3)
420 #define VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_BIT_IDX(val) vBIT(val, 61, 3)
422 #define VXGE_HAL_RXD_CFG4_1BM_L3C_QWOFF(val) vBIT(val, 5, 3)
423 #define VXGE_HAL_RXD_CFG4_1BM_L3C_WOFF(val) vBIT(val, 14, 2)
424 #define VXGE_HAL_RXD_CFG4_1BM_L4C_QWOFF(val) vBIT(val, 21, 3)
425 #define VXGE_HAL_RXD_CFG4_1BM_L4C_WOFF(val) vBIT(val, 30, 2)
426 #define VXGE_HAL_RXD_CFG4_1BM_VTAG_QWOFF(val) vBIT(val, 37, 3)
427 #define VXGE_HAL_RXD_CFG4_1BM_VTAG_WOFF(val) vBIT(val, 46, 2)
428 #define VXGE_HAL_RXD_CFG4_1BM_RTH_INFO_QWOFF(val) vBIT(val, 53, 3)
429 #define VXGE_HAL_RXD_CFG4_1BM_RTH_INFO_BOFF(val) vBIT(val, 61, 3)
431 #define VXGE_HAL_RXD_CFG_3BM_QW_SIZE(val) vBIT(val, 5, 3)
432 #define VXGE_HAL_RXD_CFG_3BM_QW2WRITE(val) vBIT(val, 8, 8)
433 #define VXGE_HAL_RXD_CFG_3BM_HCW_QWOFF(val) vBIT(val, 21, 3)
434 #define VXGE_HAL_RXD_CFG_3BM_RTH_VAL_QWOFF(val) vBIT(val, 29, 3)
435 #define VXGE_HAL_RXD_CFG_3BM_RTH_VAL_W0OFF(val) vBIT(val, 38, 2)
436 #define VXGE_HAL_RXD_CFG_3BM_RTH_VAL_W1OFF(val) vBIT(val, 46, 2)
437 #define VXGE_HAL_RXD_CFG_3BM_HEAD_OWN_QWOFF(val) vBIT(val, 53, 3)
438 #define VXGE_HAL_RXD_CFG_3BM_HEAD_OWN_BOFF(val) vBIT(val, 61, 3)
440 #define VXGE_HAL_RXD_CFG1_3BM_BUFF1_SIZE_QWOFF(val) vBIT(val, 5, 3)
441 #define VXGE_HAL_RXD_CFG1_3BM_BUFF2_SIZE_QWOFF(val) vBIT(val, 13, 3)
442 #define VXGE_HAL_RXD_CFG1_3BM_BUFF3_SIZE_QWOFF(val) vBIT(val, 21, 3)
443 #define VXGE_HAL_RXD_CFG1_3BM_TRSF_CODE_QWOFF(val) vBIT(val, 45, 3)
444 #define VXGE_HAL_RXD_CFG1_3BM_TRSF_CODE_BOFF(val) vBIT(val, 53, 3)
445 #define VXGE_HAL_RXD_CFG1_3BM_RTH_BUCKET_DATA_QWOF(val) vBIT(val, 61, 3)
447 #define VXGE_HAL_RXD_CFG2_3BM_RTH_BUCKET_DATA_BOFF(val) vBIT(val, 5, 3)
448 #define VXGE_HAL_RXD_CFG2_3BM_BUFF1_SIZE_WOFF(val) vBIT(val, 14, 2)
449 #define VXGE_HAL_RXD_CFG2_3BM_BUFF2_SIZE_WOFF(val) vBIT(val, 22, 2)
450 #define VXGE_HAL_RXD_CFG2_3BM_BUFF3_SIZE_WOFF(val) vBIT(val, 30, 2)
451 #define VXGE_HAL_RXD_CFG2_3BM_FRM_INFO_QWOFF(val) vBIT(val, 53, 3)
452 #define VXGE_HAL_RXD_CFG2_3BM_FRM_INFO_BOFF(val) vBIT(val, 61, 3)
454 #define VXGE_HAL_RXD_CFG3_3BM_BUFF1_PTR_QWOFF(val) vBIT(val, 5, 3)
455 #define VXGE_HAL_RXD_CFG3_3BM_BUFF2_PTR_QWOFF(val) vBIT(val, 13, 3)
456 #define VXGE_HAL_RXD_CFG3_3BM_BUFF3_PTR_QWOFF(val) vBIT(val, 21, 3)
457 #define VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_QWOFF(val) vBIT(val, 45, 3)
458 #define VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_BOFF(val) vBIT(val, 53, 3)
459 #define VXGE_HAL_RXD_CFG3_3BM_HEAD_OWN_BIT_IDX(val) vBIT(val, 57, 3)
460 #define VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_BIT_IDX(val) vBIT(val, 61, 3)
462 #define VXGE_HAL_RXD_CFG4_3BM_L3C_QWOFF(val) vBIT(val, 5, 3)
463 #define VXGE_HAL_RXD_CFG4_3BM_L3C_WOFF(val) vBIT(val, 14, 2)
464 #define VXGE_HAL_RXD_CFG4_3BM_L4C_QWOFF(val) vBIT(val, 21, 3)
465 #define VXGE_HAL_RXD_CFG4_3BM_L4C_WOFF(val) vBIT(val, 30, 2)
466 #define VXGE_HAL_RXD_CFG4_3BM_VTAG_QWOFF(val) vBIT(val, 37, 3)
467 #define VXGE_HAL_RXD_CFG4_3BM_VTAG_WOFF(val) vBIT(val, 46, 2)
468 #define VXGE_HAL_RXD_CFG4_3BM_RTH_INFO_QWOFF(val) vBIT(val, 53, 3)
469 #define VXGE_HAL_RXD_CFG4_3BM_RTH_INFO_BOFF(val) vBIT(val, 61, 3)
471 #define VXGE_HAL_RXD_CFG_5BM_QW_SIZE(val) vBIT(val, 5, 3)
472 #define VXGE_HAL_RXD_CFG_5BM_QW2WRITE(val) vBIT(val, 8, 8)
473 #define VXGE_HAL_RXD_CFG_5BM_HCW_QWOFF(val) vBIT(val, 21, 3)
474 #define VXGE_HAL_RXD_CFG_5BM_RTH_VAL_QWOFF(val) vBIT(val, 29, 3)
475 #define VXGE_HAL_RXD_CFG_5BM_RTH_VAL_W0OFF(val) vBIT(val, 38, 2)
476 #define VXGE_HAL_RXD_CFG_5BM_RTH_VAL_W1OFF(val) vBIT(val, 46, 2)
477 #define VXGE_HAL_RXD_CFG_5BM_HEAD_OWN_QWOFF(val) vBIT(val, 53, 3)
478 #define VXGE_HAL_RXD_CFG_5BM_HEAD_OWN_BOFF(val) vBIT(val, 61, 3)
480 #define VXGE_HAL_RXD_CFG1_5BM_BUFF1_SIZE_QWOFF(val) vBIT(val, 5, 3)
481 #define VXGE_HAL_RXD_CFG1_5BM_BUFF2_SIZE_QWOFF(val) vBIT(val, 13, 3)
482 #define VXGE_HAL_RXD_CFG1_5BM_BUFF3_SIZE_QWOFF(val) vBIT(val, 21, 3)
483 #define VXGE_HAL_RXD_CFG1_5BM_BUFF4_SIZE_QWOFF(val) vBIT(val, 29, 3)
484 #define VXGE_HAL_RXD_CFG1_5BM_BUFF5_SIZE_QWOFF(val) vBIT(val, 37, 3)
485 #define VXGE_HAL_RXD_CFG1_5BM_TRSF_CODE_QWOFF(val) vBIT(val, 45, 3)
486 #define VXGE_HAL_RXD_CFG1_5BM_TRSF_CODE_BOFF(val) vBIT(val, 53, 3)
487 #define VXGE_HAL_RXD_CFG1_5BM_RTH_BUCKET_DATA_QWOF(val) vBIT(val, 61, 3)
489 #define VXGE_HAL_RXD_CFG2_5BM_RTH_BUCKET_DATA_BOFF(val) vBIT(val, 5, 3)
490 #define VXGE_HAL_RXD_CFG2_5BM_BUFF1_SIZE_WOFF(val) vBIT(val, 14, 2)
491 #define VXGE_HAL_RXD_CFG2_5BM_BUFF2_SIZE_WOFF(val) vBIT(val, 22, 2)
492 #define VXGE_HAL_RXD_CFG2_5BM_BUFF3_SIZE_WOFF(val) vBIT(val, 30, 2)
493 #define VXGE_HAL_RXD_CFG2_5BM_BUFF4_SIZE_WOFF(val) vBIT(val, 38, 2)
494 #define VXGE_HAL_RXD_CFG2_5BM_BUFF5_SIZE_WOFF(val) vBIT(val, 46, 2)
495 #define VXGE_HAL_RXD_CFG2_5BM_FRM_INFO_QWOFF(val) vBIT(val, 53, 3)
496 #define VXGE_HAL_RXD_CFG2_5BM_FRM_INFO_BOFF(val) vBIT(val, 61, 3)
498 #define VXGE_HAL_RXD_CFG3_5BM_BUFF1_PTR_QWOFF(val) vBIT(val, 5, 3)
499 #define VXGE_HAL_RXD_CFG3_5BM_BUFF2_PTR_QWOFF(val) vBIT(val, 13, 3)
500 #define VXGE_HAL_RXD_CFG3_5BM_BUFF3_PTR_QWOFF(val) vBIT(val, 21, 3)
501 #define VXGE_HAL_RXD_CFG3_5BM_BUFF4_PTR_QWOFF(val) vBIT(val, 29, 3)
502 #define VXGE_HAL_RXD_CFG3_5BM_BUFF5_PTR_QWOFF(val) vBIT(val, 37, 3)
503 #define VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_QWOFF(val) vBIT(val, 45, 3)
504 #define VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_BOFF(val) vBIT(val, 53, 3)
505 #define VXGE_HAL_RXD_CFG3_5BM_HEAD_OWN_BIT_IDX(val) vBIT(val, 57, 3)
506 #define VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_BIT_IDX(val) vBIT(val, 61, 3)
508 #define VXGE_HAL_RXD_CFG4_5BM_L3C_QWOFF(val) vBIT(val, 5, 3)
509 #define VXGE_HAL_RXD_CFG4_5BM_L3C_WOFF(val) vBIT(val, 14, 2)
510 #define VXGE_HAL_RXD_CFG4_5BM_L4C_QWOFF(val) vBIT(val, 21, 3)
511 #define VXGE_HAL_RXD_CFG4_5BM_L4C_WOFF(val) vBIT(val, 30, 2)
512 #define VXGE_HAL_RXD_CFG4_5BM_VTAG_QWOFF(val) vBIT(val, 37, 3)
513 #define VXGE_HAL_RXD_CFG4_5BM_VTAG_WOFF(val) vBIT(val, 46, 2)
514 #define VXGE_HAL_RXD_CFG4_5BM_RTH_INFO_QWOFF(val) vBIT(val, 53, 3)
515 #define VXGE_HAL_RXD_CFG4_5BM_RTH_INFO_BOFF(val) vBIT(val, 61, 3)
517 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val) vBIT(val, 3, 5)
518 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vBIT(val, 11, 5)
519 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val) vBIT(val, 19, 5)
520 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val) vBIT(val, 27, 5)
521 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val) vBIT(val, 35, 5)
522 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val) vBIT(val, 43, 5)
523 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val) vBIT(val, 51, 5)
524 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val) vBIT(val, 59, 5)
526 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val) vBIT(val, 3, 5)
527 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vBIT(val, 11, 5)
528 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val) vBIT(val, 19, 5)
529 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val) vBIT(val, 27, 5)
530 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val) vBIT(val, 35, 5)
531 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val) vBIT(val, 43, 5)
532 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val) vBIT(val, 51, 5)
533 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val) vBIT(val, 59, 5)
535 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val) vBIT(val, 3, 5)
536 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) vBIT(val, 11, 5)
537 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val) vBIT(val, 19, 5)
538 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val) vBIT(val, 27, 5)
539 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val) vBIT(val, 35, 5)
540 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val) vBIT(val, 43, 5)
541 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val) vBIT(val, 51, 5)
542 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val) vBIT(val, 59, 5)
544 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val) vBIT(val, 3, 5)
545 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) vBIT(val, 11, 5)
546 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val) vBIT(val, 19, 5)
547 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val) vBIT(val, 27, 5)
548 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val) vBIT(val, 35, 5)
549 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val) vBIT(val, 43, 5)
550 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val) vBIT(val, 51, 5)
551 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val) vBIT(val, 59, 5)
553 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val) vBIT(val, 3, 5)
554 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) vBIT(val, 11, 5)
555 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val) vBIT(val, 19, 5)
556 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val) vBIT(val, 27, 5)
557 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val) vBIT(val, 35, 5)
558 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val) vBIT(val, 43, 5)
559 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val) vBIT(val, 51, 5)
560 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val) vBIT(val, 59, 5)
562 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val) vBIT(val, 3, 5)
563 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) vBIT(val, 11, 5)
564 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val) vBIT(val, 19, 5)
565 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val) vBIT(val, 27, 5)
566 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val) vBIT(val, 35, 5)
567 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val) vBIT(val, 43, 5)
568 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val) vBIT(val, 51, 5)
569 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val) vBIT(val, 59, 5)
571 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val) vBIT(val, 3, 5)
572 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) vBIT(val, 11, 5)
573 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val) vBIT(val, 19, 5)
574 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val) vBIT(val, 27, 5)
575 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val) vBIT(val, 35, 5)
576 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val) vBIT(val, 43, 5)
577 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val) vBIT(val, 51, 5)
578 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val) vBIT(val, 59, 5)
580 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val) vBIT(val, 3, 5)
581 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) vBIT(val, 11, 5)
582 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val) vBIT(val, 19, 5)
583 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val) vBIT(val, 27, 5)
584 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val) vBIT(val, 35, 5)
585 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val) vBIT(val, 43, 5)
586 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val) vBIT(val, 51, 5)
587 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val) vBIT(val, 59, 5)
589 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val) vBIT(val, 3, 5)
590 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) vBIT(val, 11, 5)
591 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val) vBIT(val, 19, 5)
592 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val) vBIT(val, 27, 5)
593 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val) vBIT(val, 35, 5)
594 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val) vBIT(val, 43, 5)
595 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val) vBIT(val, 51, 5)
596 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val) vBIT(val, 59, 5)
598 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val) vBIT(val, 3, 5)
599 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) vBIT(val, 11, 5)
600 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val) vBIT(val, 19, 5)
601 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val) vBIT(val, 27, 5)
602 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val) vBIT(val, 35, 5)
603 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val) vBIT(val, 43, 5)
604 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val) vBIT(val, 51, 5)
605 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val) vBIT(val, 59, 5)
607 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val) vBIT(val, 3, 5)
608 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) vBIT(val, 11, 5)
609 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val) vBIT(val, 19, 5)
610 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val) vBIT(val, 27, 5)
611 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val) vBIT(val, 35, 5)
612 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val) vBIT(val, 43, 5)
613 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val) vBIT(val, 51, 5)
614 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val) vBIT(val, 59, 5)
616 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val) vBIT(val, 3, 5)
617 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) vBIT(val, 11, 5)
618 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val) vBIT(val, 19, 5)
619 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val) vBIT(val, 27, 5)
620 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val) vBIT(val, 35, 5)
621 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val) vBIT(val, 43, 5)
622 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val) vBIT(val, 51, 5)
623 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val) vBIT(val, 59, 5)
625 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val) vBIT(val, 3, 5)
626 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) vBIT(val, 11, 5)
627 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val) vBIT(val, 19, 5)
628 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val) vBIT(val, 27, 5)
629 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val) vBIT(val, 35, 5)
630 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val) vBIT(val, 43, 5)
631 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val) vBIT(val, 51, 5)
632 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val) vBIT(val, 59, 5)
634 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val) vBIT(val, 3, 5)
635 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) vBIT(val, 11, 5)
636 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val) vBIT(val, 19, 5)
637 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val) vBIT(val, 27, 5)
638 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val) vBIT(val, 35, 5)
639 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val) vBIT(val, 43, 5)
640 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val) vBIT(val, 51, 5)
641 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val) vBIT(val, 59, 5)
643 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val) vBIT(val, 3, 5)
644 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) vBIT(val, 11, 5)
645 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val) vBIT(val, 19, 5)
646 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val) vBIT(val, 27, 5)
647 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val) vBIT(val, 35, 5)
648 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val) vBIT(val, 43, 5)
649 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val) vBIT(val, 51, 5)
650 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val) vBIT(val, 59, 5)
652 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val) vBIT(val, 3, 5)
653 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) vBIT(val, 11, 5)
654 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val) vBIT(val, 19, 5)
655 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val) vBIT(val, 27, 5)
656 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val) vBIT(val, 35, 5)
657 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val) vBIT(val, 43, 5)
658 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val) vBIT(val, 51, 5)
659 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val) vBIT(val, 59, 5)
661 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val) vBIT(val, 3, 5)
662 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) vBIT(val, 11, 5)
663 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val) vBIT(val, 19, 5)
664 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val) vBIT(val, 27, 5)
665 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val) vBIT(val, 35, 5)
666 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val) vBIT(val, 43, 5)
667 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val) vBIT(val, 51, 5)
668 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val) vBIT(val, 59, 5)
670 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val) vBIT(val, 3, 5)
671 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) vBIT(val, 11, 5)
672 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val) vBIT(val, 19, 5)
673 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val) vBIT(val, 27, 5)
674 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val) vBIT(val, 35, 5)
675 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val) vBIT(val, 43, 5)
676 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val) vBIT(val, 51, 5)
677 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val) vBIT(val, 59, 5)
679 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val) vBIT(val, 3, 5)
680 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) vBIT(val, 11, 5)
681 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val) vBIT(val, 19, 5)
682 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val) vBIT(val, 27, 5)
683 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val) vBIT(val, 35, 5)
684 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val) vBIT(val, 43, 5)
685 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val) vBIT(val, 51, 5)
686 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val) vBIT(val, 59, 5)
688 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val) vBIT(val, 3, 5)
689 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) vBIT(val, 11, 5)
690 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val) vBIT(val, 19, 5)
691 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val) vBIT(val, 27, 5)
692 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val) vBIT(val, 35, 5)
693 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val) vBIT(val, 43, 5)
694 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val) vBIT(val, 51, 5)
695 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val) vBIT(val, 59, 5)
697 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val) vBIT(val, 3, 5)
698 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) vBIT(val, 11, 5)
699 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val) vBIT(val, 19, 5)
700 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val) vBIT(val, 27, 5)
701 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val) vBIT(val, 35, 5)
702 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val) vBIT(val, 43, 5)
703 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val) vBIT(val, 51, 5)
704 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val) vBIT(val, 59, 5)
706 #define VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val) vBIT(val, 3, 5)
707 #define VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) vBIT(val, 11, 5)
708 #define VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val) vBIT(val, 19, 5)
710 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val) vBIT(val, 3, 5)
711 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val) vBIT(val, 11, 5)
712 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val) vBIT(val, 19, 5)
713 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val) vBIT(val, 27, 5)
714 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val) vBIT(val, 35, 5)
715 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val) vBIT(val, 43, 5)
716 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val) vBIT(val, 51, 5)
717 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val) vBIT(val, 59, 5)
719 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val) vBIT(val, 3, 5)
720 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val) vBIT(val, 11, 5)
721 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val) vBIT(val, 19, 5)
722 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val) vBIT(val, 27, 5)
723 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val) vBIT(val, 35, 5)
724 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val) vBIT(val, 43, 5)
725 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val) vBIT(val, 51, 5)
726 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val) vBIT(val, 59, 5)
728 #define VXGE_HAL_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val) vBIT(val, 3, 5)
732 #define VXGE_HAL_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val)\
733 vBIT(val, 59, 5)
745 #define VXGE_HAL_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) vBIT(val, 2, 30)
746 #define VXGE_HAL_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vBIT(val, 32, 32)
748 #define VXGE_HAL_WDE_PRM_CTRL_SPAV_THRESHOLD(val) vBIT(val, 2, 10)
749 #define VXGE_HAL_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vBIT(val, 18, 14)
752 #define VXGE_HAL_WDE_PRM_CTRL_FB_ROW_SIZE(val) vBIT(val, 46, 2)
754 #define VXGE_HAL_NOA_CTRL_FRM_PRTY_QUOTA(val) vBIT(val, 3, 5)
755 #define VXGE_HAL_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vBIT(val, 11, 5)
757 #define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val) vBIT(val, 37, 4)
758 #define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val) vBIT(val, 45, 4)
759 #define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val) vBIT(val, 53, 4)
760 #define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val) vBIT(val, 60, 4)
775 #define VXGE_HAL_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val) vBIT(val, 10, 22)
776 #define VXGE_HAL_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vBIT(val, 39, 9)
777 #define VXGE_HAL_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val) vBIT(val, 55, 9)
826 #define VXGE_HAL_KDFC_VP_PARTITION_0_NUMBER_0(val) vBIT(val, 5, 3)
827 #define VXGE_HAL_KDFC_VP_PARTITION_0_LENGTH_0(val) vBIT(val, 17, 15)
828 #define VXGE_HAL_KDFC_VP_PARTITION_0_NUMBER_1(val) vBIT(val, 37, 3)
829 #define VXGE_HAL_KDFC_VP_PARTITION_0_LENGTH_1(val) vBIT(val, 49, 15)
831 #define VXGE_HAL_KDFC_VP_PARTITION_1_NUMBER_2(val) vBIT(val, 5, 3)
832 #define VXGE_HAL_KDFC_VP_PARTITION_1_LENGTH_2(val) vBIT(val, 17, 15)
833 #define VXGE_HAL_KDFC_VP_PARTITION_1_NUMBER_3(val) vBIT(val, 37, 3)
834 #define VXGE_HAL_KDFC_VP_PARTITION_1_LENGTH_3(val) vBIT(val, 49, 15)
836 #define VXGE_HAL_KDFC_VP_PARTITION_2_NUMBER_4(val) vBIT(val, 5, 3)
837 #define VXGE_HAL_KDFC_VP_PARTITION_2_LENGTH_4(val) vBIT(val, 17, 15)
838 #define VXGE_HAL_KDFC_VP_PARTITION_2_NUMBER_5(val) vBIT(val, 37, 3)
839 #define VXGE_HAL_KDFC_VP_PARTITION_2_LENGTH_5(val) vBIT(val, 49, 15)
841 #define VXGE_HAL_KDFC_VP_PARTITION_3_NUMBER_6(val) vBIT(val, 5, 3)
842 #define VXGE_HAL_KDFC_VP_PARTITION_3_LENGTH_6(val) vBIT(val, 17, 15)
843 #define VXGE_HAL_KDFC_VP_PARTITION_3_NUMBER_7(val) vBIT(val, 37, 3)
844 #define VXGE_HAL_KDFC_VP_PARTITION_3_LENGTH_7(val) vBIT(val, 49, 15)
846 #define VXGE_HAL_KDFC_VP_PARTITION_4_LENGTH_8(val) vBIT(val, 17, 15)
847 #define VXGE_HAL_KDFC_VP_PARTITION_4_LENGTH_9(val) vBIT(val, 49, 15)
849 #define VXGE_HAL_KDFC_VP_PARTITION_5_LENGTH_10(val) vBIT(val, 17, 15)
850 #define VXGE_HAL_KDFC_VP_PARTITION_5_LENGTH_11(val) vBIT(val, 49, 15)
852 #define VXGE_HAL_KDFC_VP_PARTITION_6_LENGTH_12(val) vBIT(val, 17, 15)
853 #define VXGE_HAL_KDFC_VP_PARTITION_6_LENGTH_13(val) vBIT(val, 49, 15)
855 #define VXGE_HAL_KDFC_VP_PARTITION_7_LENGTH_14(val) vBIT(val, 17, 15)
856 #define VXGE_HAL_KDFC_VP_PARTITION_7_LENGTH_15(val) vBIT(val, 49, 15)
858 #define VXGE_HAL_KDFC_VP_PARTITION_8_LENGTH_16(val) vBIT(val, 17, 15)
860 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val) vBIT(val, 3, 5)
861 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val) vBIT(val, 11, 5)
862 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val) vBIT(val, 19, 5)
863 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val) vBIT(val, 27, 5)
864 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val) vBIT(val, 35, 5)
865 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val) vBIT(val, 43, 5)
866 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val) vBIT(val, 51, 5)
867 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val) vBIT(val, 59, 5)
869 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_8(val) vBIT(val, 3, 5)
870 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_9(val) vBIT(val, 11, 5)
871 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_10(val) vBIT(val, 19, 5)
872 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_11(val) vBIT(val, 27, 5)
873 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_12(val) vBIT(val, 35, 5)
874 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_13(val) vBIT(val, 43, 5)
875 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_14(val) vBIT(val, 51, 5)
876 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_15(val) vBIT(val, 59, 5)
878 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_16(val) vBIT(val, 3, 5)
879 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_17(val) vBIT(val, 11, 5)
880 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_18(val) vBIT(val, 19, 5)
881 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_19(val) vBIT(val, 27, 5)
882 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_20(val) vBIT(val, 35, 5)
883 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_21(val) vBIT(val, 43, 5)
884 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_22(val) vBIT(val, 51, 5)
885 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_23(val) vBIT(val, 59, 5)
887 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_24(val) vBIT(val, 3, 5)
888 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_25(val) vBIT(val, 11, 5)
889 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_26(val) vBIT(val, 19, 5)
890 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_27(val) vBIT(val, 27, 5)
891 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_28(val) vBIT(val, 35, 5)
892 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_29(val) vBIT(val, 43, 5)
893 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_30(val) vBIT(val, 51, 5)
894 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_31(val) vBIT(val, 59, 5)
896 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_32(val) vBIT(val, 3, 5)
897 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_33(val) vBIT(val, 11, 5)
898 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_34(val) vBIT(val, 19, 5)
899 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_35(val) vBIT(val, 27, 5)
900 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_36(val) vBIT(val, 35, 5)
901 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_37(val) vBIT(val, 43, 5)
902 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_38(val) vBIT(val, 51, 5)
903 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_39(val) vBIT(val, 59, 5)
905 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_40(val) vBIT(val, 3, 5)
906 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_41(val) vBIT(val, 11, 5)
907 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_42(val) vBIT(val, 19, 5)
908 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_43(val) vBIT(val, 27, 5)
909 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_44(val) vBIT(val, 35, 5)
910 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_45(val) vBIT(val, 43, 5)
911 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_46(val) vBIT(val, 51, 5)
912 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_47(val) vBIT(val, 59, 5)
914 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_48(val) vBIT(val, 3, 5)
915 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_49(val) vBIT(val, 11, 5)
916 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_50(val) vBIT(val, 19, 5)
917 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_51(val) vBIT(val, 27, 5)
918 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_52(val) vBIT(val, 35, 5)
919 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_53(val) vBIT(val, 43, 5)
920 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_54(val) vBIT(val, 51, 5)
921 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_55(val) vBIT(val, 59, 5)
923 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_56(val) vBIT(val, 3, 5)
924 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_57(val) vBIT(val, 11, 5)
925 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_58(val) vBIT(val, 19, 5)
926 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_59(val) vBIT(val, 27, 5)
927 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_60(val) vBIT(val, 35, 5)
928 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_61(val) vBIT(val, 43, 5)
929 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_62(val) vBIT(val, 51, 5)
930 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_63(val) vBIT(val, 59, 5)
932 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_64(val) vBIT(val, 3, 5)
933 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_65(val) vBIT(val, 11, 5)
934 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_66(val) vBIT(val, 19, 5)
935 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_67(val) vBIT(val, 27, 5)
936 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_68(val) vBIT(val, 35, 5)
937 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_69(val) vBIT(val, 43, 5)
938 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_70(val) vBIT(val, 51, 5)
939 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_71(val) vBIT(val, 59, 5)
941 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_72(val) vBIT(val, 3, 5)
942 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_73(val) vBIT(val, 11, 5)
943 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_74(val) vBIT(val, 19, 5)
944 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_75(val) vBIT(val, 27, 5)
945 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_76(val) vBIT(val, 35, 5)
946 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_77(val) vBIT(val, 43, 5)
947 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_78(val) vBIT(val, 51, 5)
948 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_79(val) vBIT(val, 59, 5)
950 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_80(val) vBIT(val, 3, 5)
951 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_81(val) vBIT(val, 11, 5)
952 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_82(val) vBIT(val, 19, 5)
953 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_83(val) vBIT(val, 27, 5)
954 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_84(val) vBIT(val, 35, 5)
955 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_85(val) vBIT(val, 43, 5)
956 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_86(val) vBIT(val, 51, 5)
957 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_87(val) vBIT(val, 59, 5)
959 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_88(val) vBIT(val, 3, 5)
960 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_89(val) vBIT(val, 11, 5)
961 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_90(val) vBIT(val, 19, 5)
962 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_91(val) vBIT(val, 27, 5)
963 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_92(val) vBIT(val, 35, 5)
964 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_93(val) vBIT(val, 43, 5)
965 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_94(val) vBIT(val, 51, 5)
966 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_95(val) vBIT(val, 59, 5)
968 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_96(val) vBIT(val, 3, 5)
969 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_97(val) vBIT(val, 11, 5)
970 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_98(val) vBIT(val, 19, 5)
971 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_99(val) vBIT(val, 27, 5)
972 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_100(val) vBIT(val, 35, 5)
973 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_101(val) vBIT(val, 43, 5)
974 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_102(val) vBIT(val, 51, 5)
975 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_103(val) vBIT(val, 59, 5)
977 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_104(val) vBIT(val, 3, 5)
978 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_105(val) vBIT(val, 11, 5)
979 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_106(val) vBIT(val, 19, 5)
980 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_107(val) vBIT(val, 27, 5)
981 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_108(val) vBIT(val, 35, 5)
982 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_109(val) vBIT(val, 43, 5)
983 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_110(val) vBIT(val, 51, 5)
984 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_111(val) vBIT(val, 59, 5)
986 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_112(val) vBIT(val, 3, 5)
987 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_113(val) vBIT(val, 11, 5)
988 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_114(val) vBIT(val, 19, 5)
989 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_115(val) vBIT(val, 27, 5)
990 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_116(val) vBIT(val, 35, 5)
991 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_117(val) vBIT(val, 43, 5)
992 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_118(val) vBIT(val, 51, 5)
993 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_119(val) vBIT(val, 59, 5)
995 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_120(val) vBIT(val, 3, 5)
996 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_121(val) vBIT(val, 11, 5)
997 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_122(val) vBIT(val, 19, 5)
998 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_123(val) vBIT(val, 27, 5)
999 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_124(val) vBIT(val, 35, 5)
1000 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_125(val) vBIT(val, 43, 5)
1001 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_126(val) vBIT(val, 51, 5)
1002 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_127(val) vBIT(val, 59, 5)
1004 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_128(val) vBIT(val, 3, 5)
1005 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_129(val) vBIT(val, 11, 5)
1006 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_130(val) vBIT(val, 19, 5)
1007 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_131(val) vBIT(val, 27, 5)
1008 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_132(val) vBIT(val, 35, 5)
1009 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_133(val) vBIT(val, 43, 5)
1010 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_134(val) vBIT(val, 51, 5)
1011 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_135(val) vBIT(val, 59, 5)
1013 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_136(val) vBIT(val, 3, 5)
1014 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_137(val) vBIT(val, 11, 5)
1015 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_138(val) vBIT(val, 19, 5)
1016 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_139(val) vBIT(val, 27, 5)
1017 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_140(val) vBIT(val, 35, 5)
1018 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_141(val) vBIT(val, 43, 5)
1019 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_142(val) vBIT(val, 51, 5)
1020 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_143(val) vBIT(val, 59, 5)
1022 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_144(val) vBIT(val, 3, 5)
1023 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_145(val) vBIT(val, 11, 5)
1024 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_146(val) vBIT(val, 19, 5)
1025 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_147(val) vBIT(val, 27, 5)
1026 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_148(val) vBIT(val, 35, 5)
1027 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_149(val) vBIT(val, 43, 5)
1028 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_150(val) vBIT(val, 51, 5)
1029 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_151(val) vBIT(val, 59, 5)
1031 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_19_NUMBER_152(val) vBIT(val, 3, 5)
1033 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val) vBIT(val, 3, 5)
1034 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val) vBIT(val, 11, 5)
1035 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val) vBIT(val, 19, 5)
1036 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val) vBIT(val, 27, 5)
1037 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val) vBIT(val, 35, 5)
1038 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val) vBIT(val, 43, 5)
1039 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val) vBIT(val, 51, 5)
1040 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val) vBIT(val, 59, 5)
1042 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_8(val) vBIT(val, 3, 5)
1043 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_9(val) vBIT(val, 11, 5)
1044 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_10(val) vBIT(val, 19, 5)
1045 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_11(val) vBIT(val, 27, 5)
1046 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_12(val) vBIT(val, 35, 5)
1047 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_13(val) vBIT(val, 43, 5)
1048 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_14(val) vBIT(val, 51, 5)
1049 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_15(val) vBIT(val, 59, 5)
1051 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_16(val) vBIT(val, 3, 5)
1052 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_17(val) vBIT(val, 11, 5)
1053 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_18(val) vBIT(val, 19, 5)
1054 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_19(val) vBIT(val, 27, 5)
1055 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_20(val) vBIT(val, 35, 5)
1056 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_21(val) vBIT(val, 43, 5)
1057 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_22(val) vBIT(val, 51, 5)
1058 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_23(val) vBIT(val, 59, 5)
1060 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_24(val) vBIT(val, 3, 5)
1061 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_25(val) vBIT(val, 11, 5)
1062 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_26(val) vBIT(val, 19, 5)
1063 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_27(val) vBIT(val, 27, 5)
1064 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_28(val) vBIT(val, 35, 5)
1065 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_29(val) vBIT(val, 43, 5)
1066 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_30(val) vBIT(val, 51, 5)
1067 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_31(val) vBIT(val, 59, 5)
1069 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_32(val) vBIT(val, 3, 5)
1070 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_33(val) vBIT(val, 11, 5)
1071 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_34(val) vBIT(val, 19, 5)
1072 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_35(val) vBIT(val, 27, 5)
1073 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_36(val) vBIT(val, 35, 5)
1074 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_37(val) vBIT(val, 43, 5)
1075 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_38(val) vBIT(val, 51, 5)
1076 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_39(val) vBIT(val, 59, 5)
1078 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_40(val) vBIT(val, 3, 5)
1079 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_41(val) vBIT(val, 11, 5)
1080 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_42(val) vBIT(val, 19, 5)
1081 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_43(val) vBIT(val, 27, 5)
1082 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_44(val) vBIT(val, 35, 5)
1083 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_45(val) vBIT(val, 43, 5)
1084 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_46(val) vBIT(val, 51, 5)
1085 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_47(val) vBIT(val, 59, 5)
1087 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_48(val) vBIT(val, 3, 5)
1088 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_49(val) vBIT(val, 11, 5)
1089 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_50(val) vBIT(val, 19, 5)
1090 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_51(val) vBIT(val, 27, 5)
1091 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_52(val) vBIT(val, 35, 5)
1092 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_53(val) vBIT(val, 43, 5)
1093 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_54(val) vBIT(val, 51, 5)
1094 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_55(val) vBIT(val, 59, 5)
1096 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_56(val) vBIT(val, 3, 5)
1097 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_57(val) vBIT(val, 11, 5)
1098 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_58(val) vBIT(val, 19, 5)
1099 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_59(val) vBIT(val, 27, 5)
1100 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_60(val) vBIT(val, 35, 5)
1101 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_61(val) vBIT(val, 43, 5)
1102 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_62(val) vBIT(val, 51, 5)
1103 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_63(val) vBIT(val, 59, 5)
1105 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_64(val) vBIT(val, 3, 5)
1106 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_65(val) vBIT(val, 11, 5)
1107 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_66(val) vBIT(val, 19, 5)
1108 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_67(val) vBIT(val, 27, 5)
1109 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_68(val) vBIT(val, 35, 5)
1110 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_69(val) vBIT(val, 43, 5)
1111 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_70(val) vBIT(val, 51, 5)
1112 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_71(val) vBIT(val, 59, 5)
1114 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_72(val) vBIT(val, 3, 5)
1115 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_73(val) vBIT(val, 11, 5)
1116 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_74(val) vBIT(val, 19, 5)
1117 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_75(val) vBIT(val, 27, 5)
1118 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_76(val) vBIT(val, 35, 5)
1119 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_77(val) vBIT(val, 43, 5)
1120 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_78(val) vBIT(val, 51, 5)
1121 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_79(val) vBIT(val, 59, 5)
1123 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_80(val) vBIT(val, 3, 5)
1124 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_81(val) vBIT(val, 11, 5)
1125 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_82(val) vBIT(val, 19, 5)
1126 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_83(val) vBIT(val, 27, 5)
1127 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_84(val) vBIT(val, 35, 5)
1128 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_85(val) vBIT(val, 43, 5)
1129 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_86(val) vBIT(val, 51, 5)
1130 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_87(val) vBIT(val, 59, 5)
1132 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_88(val) vBIT(val, 3, 5)
1133 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_89(val) vBIT(val, 11, 5)
1134 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_90(val) vBIT(val, 19, 5)
1135 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_91(val) vBIT(val, 27, 5)
1136 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_92(val) vBIT(val, 35, 5)
1137 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_93(val) vBIT(val, 43, 5)
1138 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_94(val) vBIT(val, 51, 5)
1139 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_95(val) vBIT(val, 59, 5)
1141 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_96(val) vBIT(val, 3, 5)
1142 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_97(val) vBIT(val, 11, 5)
1143 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_98(val) vBIT(val, 19, 5)
1144 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_99(val) vBIT(val, 27, 5)
1145 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_100(val) vBIT(val, 35, 5)
1146 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_101(val) vBIT(val, 43, 5)
1147 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_102(val) vBIT(val, 51, 5)
1148 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_103(val) vBIT(val, 59, 5)
1150 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_104(val) vBIT(val, 3, 5)
1151 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_105(val) vBIT(val, 11, 5)
1152 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_106(val) vBIT(val, 19, 5)
1153 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_107(val) vBIT(val, 27, 5)
1154 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_108(val) vBIT(val, 35, 5)
1155 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_109(val) vBIT(val, 43, 5)
1156 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_110(val) vBIT(val, 51, 5)
1157 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_111(val) vBIT(val, 59, 5)
1159 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_112(val) vBIT(val, 3, 5)
1160 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_113(val) vBIT(val, 11, 5)
1161 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_114(val) vBIT(val, 19, 5)
1162 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_115(val) vBIT(val, 27, 5)
1163 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_116(val) vBIT(val, 35, 5)
1164 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_117(val) vBIT(val, 43, 5)
1165 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_118(val) vBIT(val, 51, 5)
1166 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_119(val) vBIT(val, 59, 5)
1168 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_120(val) vBIT(val, 3, 5)
1169 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_121(val) vBIT(val, 11, 5)
1170 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_122(val) vBIT(val, 19, 5)
1171 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_123(val) vBIT(val, 27, 5)
1172 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_124(val) vBIT(val, 35, 5)
1173 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_125(val) vBIT(val, 43, 5)
1174 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_126(val) vBIT(val, 51, 5)
1175 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_127(val) vBIT(val, 59, 5)
1177 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_128(val) vBIT(val, 3, 5)
1178 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_129(val) vBIT(val, 11, 5)
1179 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_130(val) vBIT(val, 19, 5)
1180 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_131(val) vBIT(val, 27, 5)
1181 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_132(val) vBIT(val, 35, 5)
1182 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_133(val) vBIT(val, 43, 5)
1183 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_134(val) vBIT(val, 51, 5)
1184 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_135(val) vBIT(val, 59, 5)
1186 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_136(val) vBIT(val, 3, 5)
1187 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_137(val) vBIT(val, 11, 5)
1188 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_138(val) vBIT(val, 19, 5)
1189 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_139(val) vBIT(val, 27, 5)
1190 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_140(val) vBIT(val, 35, 5)
1191 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_141(val) vBIT(val, 43, 5)
1192 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_142(val) vBIT(val, 51, 5)
1193 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_143(val) vBIT(val, 59, 5)
1195 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_144(val) vBIT(val, 3, 5)
1196 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_145(val) vBIT(val, 11, 5)
1197 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_146(val) vBIT(val, 19, 5)
1198 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_147(val) vBIT(val, 27, 5)
1199 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_148(val) vBIT(val, 35, 5)
1200 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_149(val) vBIT(val, 43, 5)
1201 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_150(val) vBIT(val, 51, 5)
1202 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_151(val) vBIT(val, 59, 5)
1204 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_39_NUMBER_152(val) vBIT(val, 3, 5)
1206 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val) vBIT(val, 3, 5)
1207 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val) vBIT(val, 11, 5)
1208 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val) vBIT(val, 19, 5)
1209 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val) vBIT(val, 27, 5)
1210 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val) vBIT(val, 35, 5)
1211 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val) vBIT(val, 43, 5)
1212 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val) vBIT(val, 51, 5)
1213 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val) vBIT(val, 59, 5)
1215 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_8(val) vBIT(val, 3, 5)
1216 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_9(val) vBIT(val, 11, 5)
1217 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_10(val) vBIT(val, 19, 5)
1218 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_11(val) vBIT(val, 27, 5)
1219 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_12(val) vBIT(val, 35, 5)
1220 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_13(val) vBIT(val, 43, 5)
1221 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_14(val) vBIT(val, 51, 5)
1222 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_15(val) vBIT(val, 59, 5)
1224 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_16(val) vBIT(val, 3, 5)
1225 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_17(val) vBIT(val, 11, 5)
1226 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_18(val) vBIT(val, 19, 5)
1227 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_19(val) vBIT(val, 27, 5)
1228 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_20(val) vBIT(val, 35, 5)
1229 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_21(val) vBIT(val, 43, 5)
1230 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_22(val) vBIT(val, 51, 5)
1231 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_23(val) vBIT(val, 59, 5)
1233 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_24(val) vBIT(val, 3, 5)
1234 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_25(val) vBIT(val, 11, 5)
1235 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_26(val) vBIT(val, 19, 5)
1236 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_27(val) vBIT(val, 27, 5)
1237 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_28(val) vBIT(val, 35, 5)
1238 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_29(val) vBIT(val, 43, 5)
1239 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_30(val) vBIT(val, 51, 5)
1240 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_31(val) vBIT(val, 59, 5)
1242 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_32(val) vBIT(val, 3, 5)
1243 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_33(val) vBIT(val, 11, 5)
1244 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_34(val) vBIT(val, 19, 5)
1245 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_35(val) vBIT(val, 27, 5)
1246 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_36(val) vBIT(val, 35, 5)
1247 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_37(val) vBIT(val, 43, 5)
1248 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_38(val) vBIT(val, 51, 5)
1249 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_39(val) vBIT(val, 59, 5)
1251 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_40(val) vBIT(val, 3, 5)
1252 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_41(val) vBIT(val, 11, 5)
1253 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_42(val) vBIT(val, 19, 5)
1254 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_43(val) vBIT(val, 27, 5)
1255 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_44(val) vBIT(val, 35, 5)
1256 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_45(val) vBIT(val, 43, 5)
1257 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_46(val) vBIT(val, 51, 5)
1258 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_47(val) vBIT(val, 59, 5)
1260 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_48(val) vBIT(val, 3, 5)
1261 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_49(val) vBIT(val, 11, 5)
1262 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_50(val) vBIT(val, 19, 5)
1263 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_51(val) vBIT(val, 27, 5)
1264 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_52(val) vBIT(val, 35, 5)
1265 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_53(val) vBIT(val, 43, 5)
1266 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_54(val) vBIT(val, 51, 5)
1267 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_55(val) vBIT(val, 59, 5)
1269 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_56(val) vBIT(val, 3, 5)
1270 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_57(val) vBIT(val, 11, 5)
1271 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_58(val) vBIT(val, 19, 5)
1272 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_59(val) vBIT(val, 27, 5)
1273 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_60(val) vBIT(val, 35, 5)
1274 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_61(val) vBIT(val, 43, 5)
1275 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_62(val) vBIT(val, 51, 5)
1276 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_63(val) vBIT(val, 59, 5)
1278 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_64(val) vBIT(val, 3, 5)
1279 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_65(val) vBIT(val, 11, 5)
1280 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_66(val) vBIT(val, 19, 5)
1281 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_67(val) vBIT(val, 27, 5)
1282 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_68(val) vBIT(val, 35, 5)
1283 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_69(val) vBIT(val, 43, 5)
1284 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_70(val) vBIT(val, 51, 5)
1285 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_71(val) vBIT(val, 59, 5)
1287 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_72(val) vBIT(val, 3, 5)
1288 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_73(val) vBIT(val, 11, 5)
1289 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_74(val) vBIT(val, 19, 5)
1290 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_75(val) vBIT(val, 27, 5)
1291 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_76(val) vBIT(val, 35, 5)
1292 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_77(val) vBIT(val, 43, 5)
1293 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_78(val) vBIT(val, 51, 5)
1294 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_79(val) vBIT(val, 59, 5)
1296 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_80(val) vBIT(val, 3, 5)
1297 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_81(val) vBIT(val, 11, 5)
1298 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_82(val) vBIT(val, 19, 5)
1299 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_83(val) vBIT(val, 27, 5)
1300 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_84(val) vBIT(val, 35, 5)
1301 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_85(val) vBIT(val, 43, 5)
1302 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_86(val) vBIT(val, 51, 5)
1303 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_87(val) vBIT(val, 59, 5)
1305 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_88(val) vBIT(val, 3, 5)
1306 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_89(val) vBIT(val, 11, 5)
1307 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_90(val) vBIT(val, 19, 5)
1308 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_91(val) vBIT(val, 27, 5)
1309 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_92(val) vBIT(val, 35, 5)
1310 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_93(val) vBIT(val, 43, 5)
1311 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_94(val) vBIT(val, 51, 5)
1312 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_95(val) vBIT(val, 59, 5)
1314 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_96(val) vBIT(val, 3, 5)
1315 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_97(val) vBIT(val, 11, 5)
1316 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_98(val) vBIT(val, 19, 5)
1317 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_99(val) vBIT(val, 27, 5)
1318 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_100(val) vBIT(val, 35, 5)
1319 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_101(val) vBIT(val, 43, 5)
1320 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_102(val) vBIT(val, 51, 5)
1321 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_103(val) vBIT(val, 59, 5)
1323 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_104(val) vBIT(val, 3, 5)
1324 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_105(val) vBIT(val, 11, 5)
1325 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_106(val) vBIT(val, 19, 5)
1326 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_107(val) vBIT(val, 27, 5)
1327 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_108(val) vBIT(val, 35, 5)
1328 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_109(val) vBIT(val, 43, 5)
1329 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_110(val) vBIT(val, 51, 5)
1330 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_111(val) vBIT(val, 59, 5)
1332 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_112(val) vBIT(val, 3, 5)
1333 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_113(val) vBIT(val, 11, 5)
1334 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_114(val) vBIT(val, 19, 5)
1335 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_115(val) vBIT(val, 27, 5)
1336 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_116(val) vBIT(val, 35, 5)
1337 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_117(val) vBIT(val, 43, 5)
1338 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_118(val) vBIT(val, 51, 5)
1339 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_119(val) vBIT(val, 59, 5)
1341 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_120(val) vBIT(val, 3, 5)
1342 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_121(val) vBIT(val, 11, 5)
1343 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_122(val) vBIT(val, 19, 5)
1344 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_123(val) vBIT(val, 27, 5)
1345 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_124(val) vBIT(val, 35, 5)
1346 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_125(val) vBIT(val, 43, 5)
1347 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_126(val) vBIT(val, 51, 5)
1348 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_127(val) vBIT(val, 59, 5)
1350 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_128(val) vBIT(val, 3, 5)
1351 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_129(val) vBIT(val, 11, 5)
1352 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_130(val) vBIT(val, 19, 5)
1353 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_131(val) vBIT(val, 27, 5)
1354 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_132(val) vBIT(val, 35, 5)
1355 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_133(val) vBIT(val, 43, 5)
1356 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_134(val) vBIT(val, 51, 5)
1357 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_135(val) vBIT(val, 59, 5)
1359 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_136(val) vBIT(val, 3, 5)
1360 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_137(val) vBIT(val, 11, 5)
1361 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_138(val) vBIT(val, 19, 5)
1362 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_139(val) vBIT(val, 27, 5)
1363 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_140(val) vBIT(val, 35, 5)
1364 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_141(val) vBIT(val, 43, 5)
1365 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_142(val) vBIT(val, 51, 5)
1366 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_143(val) vBIT(val, 59, 5)
1368 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_144(val) vBIT(val, 3, 5)
1369 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_145(val) vBIT(val, 11, 5)
1370 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_146(val) vBIT(val, 19, 5)
1371 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_147(val) vBIT(val, 27, 5)
1372 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_148(val) vBIT(val, 35, 5)
1373 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_149(val) vBIT(val, 43, 5)
1374 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_150(val) vBIT(val, 51, 5)
1375 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_151(val) vBIT(val, 59, 5)
1377 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_59_NUMBER_152(val) vBIT(val, 3, 5)
1379 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val) vBIT(val, 6, 2)
1380 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val) vBIT(val, 14, 2)
1381 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val) vBIT(val, 22, 2)
1382 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val) vBIT(val, 30, 2)
1383 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val) vBIT(val, 38, 2)
1384 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val) vBIT(val, 46, 2)
1385 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val) vBIT(val, 54, 2)
1386 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val) vBIT(val, 62, 2)
1388 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val) vBIT(val, 6, 2)
1390 #define VXGE_HAL_KDFC_FIFO_0_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1392 #define VXGE_HAL_KDFC_FIFO_1_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1394 #define VXGE_HAL_KDFC_FIFO_2_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1396 #define VXGE_HAL_KDFC_FIFO_3_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1398 #define VXGE_HAL_KDFC_FIFO_4_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1400 #define VXGE_HAL_KDFC_FIFO_5_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1402 #define VXGE_HAL_KDFC_FIFO_6_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1404 #define VXGE_HAL_KDFC_FIFO_7_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1406 #define VXGE_HAL_KDFC_FIFO_8_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1408 #define VXGE_HAL_KDFC_FIFO_9_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1410 #define VXGE_HAL_KDFC_FIFO_10_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1412 #define VXGE_HAL_KDFC_FIFO_11_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1414 #define VXGE_HAL_KDFC_FIFO_12_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1416 #define VXGE_HAL_KDFC_FIFO_13_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1418 #define VXGE_HAL_KDFC_FIFO_14_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1420 #define VXGE_HAL_KDFC_FIFO_15_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1422 #define VXGE_HAL_KDFC_FIFO_16_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1424 #define VXGE_HAL_KDFC_FIFO_17_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1426 #define VXGE_HAL_KDFC_FIFO_18_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1428 #define VXGE_HAL_KDFC_FIFO_19_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1430 #define VXGE_HAL_KDFC_FIFO_20_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1432 #define VXGE_HAL_KDFC_FIFO_21_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1434 #define VXGE_HAL_KDFC_FIFO_22_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1436 #define VXGE_HAL_KDFC_FIFO_23_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1438 #define VXGE_HAL_KDFC_FIFO_24_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1440 #define VXGE_HAL_KDFC_FIFO_25_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1442 #define VXGE_HAL_KDFC_FIFO_26_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1444 #define VXGE_HAL_KDFC_FIFO_27_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1446 #define VXGE_HAL_KDFC_FIFO_28_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1448 #define VXGE_HAL_KDFC_FIFO_29_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1450 #define VXGE_HAL_KDFC_FIFO_30_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1452 #define VXGE_HAL_KDFC_FIFO_31_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1454 #define VXGE_HAL_KDFC_FIFO_32_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1456 #define VXGE_HAL_KDFC_FIFO_33_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1458 #define VXGE_HAL_KDFC_FIFO_34_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1460 #define VXGE_HAL_KDFC_FIFO_35_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1462 #define VXGE_HAL_KDFC_FIFO_36_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1464 #define VXGE_HAL_KDFC_FIFO_37_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1466 #define VXGE_HAL_KDFC_FIFO_38_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1468 #define VXGE_HAL_KDFC_FIFO_39_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1470 #define VXGE_HAL_KDFC_FIFO_40_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1472 #define VXGE_HAL_KDFC_FIFO_41_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1474 #define VXGE_HAL_KDFC_FIFO_42_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1476 #define VXGE_HAL_KDFC_FIFO_43_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1478 #define VXGE_HAL_KDFC_FIFO_44_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1480 #define VXGE_HAL_KDFC_FIFO_45_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1482 #define VXGE_HAL_KDFC_FIFO_46_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1484 #define VXGE_HAL_KDFC_FIFO_47_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1486 #define VXGE_HAL_KDFC_FIFO_48_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1488 #define VXGE_HAL_KDFC_FIFO_49_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1490 #define VXGE_HAL_KDFC_FIFO_50_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5)
1492 #define VXGE_HAL_KDFC_KRNL_USR_CTRL_CODE(val) vBIT(val, 4, 4)
1495 #define VXGE_HAL_KDFC_PDA_MONITOR_FIFO_NO(val) vBIT(val, 10, 6)
1496 #define VXGE_HAL_KDFC_PDA_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15)
1497 #define VXGE_HAL_KDFC_PDA_MONITOR_TYPE(val) vBIT(val, 32, 8)
1498 #define VXGE_HAL_KDFC_PDA_MONITOR_VP(val) vBIT(val, 43, 5)
1501 #define VXGE_HAL_KDFC_MP_MONITOR_FIFO_NO(val) vBIT(val, 10, 6)
1502 #define VXGE_HAL_KDFC_MP_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15)
1503 #define VXGE_HAL_KDFC_MP_MONITOR_TYPE(val) vBIT(val, 32, 8)
1504 #define VXGE_HAL_KDFC_MP_MONITOR_VP(val) vBIT(val, 43, 5)
1507 #define VXGE_HAL_KDFC_PE_MONITOR_FIFO_NO(val) vBIT(val, 10, 6)
1508 #define VXGE_HAL_KDFC_PE_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15)
1509 #define VXGE_HAL_KDFC_PE_MONITOR_TYPE(val) vBIT(val, 32, 8)
1510 #define VXGE_HAL_KDFC_PE_MONITOR_VP(val) vBIT(val, 43, 5)
1511 #define VXGE_HAL_KDFC_PE_MONITOR_IMM_DATA_CNT(val) vBIT(val, 48, 8)
1514 #define VXGE_HAL_KDFC_READ_CNTRL_KDFC_RDCTRL(val) vBIT(val, 14, 2)
1516 #define VXGE_HAL_KDFC_READ_CNTRL_KDFC_ADDR(val) vBIT(val, 49, 15)
1518 #define VXGE_HAL_KDFC_READ_DATA_READ_DATA(val) vBIT(val, 0, 64)
1522 #define VXGE_HAL_KDFC_MULTI_CYCLE_CTRL_MULTI_CYCLE_SEL(val) vBIT(val, 6, 2)
1545 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val)\
1546 vBIT(val, 0, 4)
1547 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val)\
1548 vBIT(val, 4, 4)
1549 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val)\
1550 vBIT(val, 8, 4)
1551 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val)\
1552 vBIT(val, 12, 4)
1553 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val)\
1554 vBIT(val, 16, 4)
1555 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val)\
1556 vBIT(val, 20, 4)
1557 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val)\
1558 vBIT(val, 24, 2)
1559 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val)\
1560 vBIT(val, 26, 2)
1561 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val)\
1562 vBIT(val, 28, 2)
1563 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val)\
1564 vBIT(val, 30, 2)
1573 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val)\
1574 vBIT(val, 40, 7)
1575 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val)\
1576 vBIT(val, 47, 7)
1577 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val)\
1578 vBIT(val, 54, 3)
1579 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val)\
1580 vBIT(val, 57, 3)
1614 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val) vBIT(val, 0, 4)
1615 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val) vBIT(val, 4, 4)
1616 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val) vBIT(val, 8, 4)
1617 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val) vBIT(val, 12, 4)
1618 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val) vBIT(val, 16, 4)
1619 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val) vBIT(val, 20, 4)
1620 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val) vBIT(val, 24, 4)
1621 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val) vBIT(val, 28, 4)
1633 #define VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val) vBIT(val, 50, 14)
1641 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val) vBIT(val, 9, 3)
1643 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val) vBIT(val, 20, 16)
1647 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val) vBIT(val, 48, 8)
1659 #define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) vBIT(val, 1, 7)
1660 #define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val) vBIT(val, 8, 4)
1661 #define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) vBIT(val, 12, 4)
1662 #define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val) vBIT(val, 16, 4)
1696 #define VXGE_HAL_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val) vBIT(val, 24, 8)
1708 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val) vBIT(val, 5, 3)
1709 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vBIT(val, 9, 3)
1710 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_L4PN(val) vBIT(val, 13, 3)
1711 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val) vBIT(val, 17, 3)
1712 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val) vBIT(val, 21, 3)
1713 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_DS(val) vBIT(val, 25, 3)
1714 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_QOS(val) vBIT(val, 29, 3)
1715 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val) vBIT(val, 33, 3)
1716 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val) vBIT(val, 37, 3)
1718 #define VXGE_HAL_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val) vBIT(val, 0, 17)
1720 #define VXGE_HAL_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) vBIT(val, 0, 17)
1725 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL(val) vBIT(val, 8, 4)
1729 #define VXGE_HAL_RTS_MGR_STEER_CTRL_OFFSET(val) vBIT(val, 35, 13)
1732 #define VXGE_HAL_RTS_MGR_STEER_DATA0_DATA(val) vBIT(val, 0, 64)
1734 #define VXGE_HAL_RTS_MGR_STEER_DATA1_DATA(val) vBIT(val, 0, 64)
1736 #define VXGE_HAL_RTS_MGR_STEER_VPATH_VECTOR_VPATH_VECTOR(val) vBIT(val, 0, 17)
1740 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_LANE_CHAR1(val) vBIT(val, 1, 3)
1742 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXD_CHAR1(val) vBIT(val, 8, 8)
1743 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_LANE_CHAR2(val) vBIT(val, 17, 3)
1745 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXD_CHAR2(val) vBIT(val, 24, 8)
1747 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_BEHAV_CHAR2_NUM_CHAR(val)\
1748 vBIT(val, 40, 16)
1751 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE0(val) vBIT(val, 8, 8)
1753 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE1(val) vBIT(val, 24, 8)
1755 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE2(val) vBIT(val, 40, 8)
1757 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE3(val) vBIT(val, 56, 8)
1760 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE0(val) vBIT(val, 8, 8)
1762 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE1(val) vBIT(val, 24, 8)
1764 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE2(val) vBIT(val, 40, 8)
1766 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE3(val) vBIT(val, 56, 8)
1769 #define VXGE_HAL_XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_NUM_COL(val) vBIT(val, 8, 16)
1774 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val) vBIT(val, 0, 8)
1775 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vBIT(val, 8, 8)
1776 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val) vBIT(val, 16, 8)
1780 #define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR0(val) vBIT(val, 0, 4)
1781 #define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR1(val) vBIT(val, 4, 4)
1782 #define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR2(val) vBIT(val, 8, 4)
1783 #define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR3(val) vBIT(val, 12, 4)
1784 #define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR0(val) vBIT(val, 16, 4)
1785 #define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR1(val) vBIT(val, 20, 4)
1786 #define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR2(val) vBIT(val, 24, 4)
1787 #define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR3(val) vBIT(val, 28, 4)
1823 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val)\
1824 vBIT(val, 40, 2)
1825 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val)\
1826 vBIT(val, 42, 2)
1827 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val)\
1828 vBIT(val, 44, 2)
1829 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val)\
1830 vBIT(val, 46, 2)
1831 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val)\
1832 vBIT(val, 48, 2)
1833 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val)\
1834 vBIT(val, 50, 2)
1835 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val)\
1836 vBIT(val, 52, 2)
1837 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val)\
1838 vBIT(val, 54, 2)
1839 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val)\
1840 vBIT(val, 56, 2)
1841 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val)\
1842 vBIT(val, 58, 2)
1884 #define VXGE_HAL_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val)\
1885 vBIT(val, 0, 17)
1887 #define VXGE_HAL_XGMAC_GEN_FW_MEMO_MASK_MASK(val) vBIT(val, 0, 64)
1889 #define VXGE_HAL_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val)\
1890 vBIT(val, 0, 17)
1894 #define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP(val) vBIT(val, 0, 4)
1895 #define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_DOWN(val) vBIT(val, 4, 4)
1896 #define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP(val) vBIT(val, 8, 4)
1897 #define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_DOWN(val) vBIT(val, 12, 4)
1906 #define VXGE_HAL_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val) vBIT(val, 2, 2)
1909 #define VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_UP(val) vBIT(val, 28, 4)
1910 #define VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val) vBIT(val, 32, 4)
1913 #define VXGE_HAL_XMAC_TIMESTAMP_USE_LINK_ID(val) vBIT(val, 6, 2)
1914 #define VXGE_HAL_XMAC_TIMESTAMP_INTERVAL(val) vBIT(val, 12, 4)
1916 #define VXGE_HAL_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vBIT(val, 32, 16)
1918 #define VXGE_HAL_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val) vBIT(val, 4, 4)
1919 #define VXGE_HAL_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vBIT(val, 8, 4)
1922 #define VXGE_HAL_XMAC_STATS_SYS_CMD_OP(val) vBIT(val, 5, 3)
1924 #define VXGE_HAL_XMAC_STATS_SYS_CMD_LOC_SEL(val) vBIT(val, 27, 5)
1925 #define VXGE_HAL_XMAC_STATS_SYS_CMD_OFFSET_SEL(val) vBIT(val, 32, 8)
1927 #define VXGE_HAL_XMAC_STATS_SYS_DATA_XSMGR_DATA(val) vBIT(val, 0, 64)
1944 #define VXGE_HAL_XMAC_STATION_ADDR_PORT_MAC_ADDR(val) vBIT(val, 0, 48)
1953 #define VXGE_HAL_LAG_CFG_MODE(val) vBIT(val, 6, 2)
1959 #define VXGE_HAL_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) vBIT(val, 8, 8)
1966 #define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val)\
1967 vBIT(val, 32, 16)
1976 #define VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER(val) vBIT(val, 0, 16)
1977 #define VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER(val) vBIT(val, 16, 16)
1978 #define VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val) vBIT(val, 32, 16)
1979 #define VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT(val) vBIT(val, 48, 16)
1981 #define VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET(val) vBIT(val, 0, 16)
1982 #define VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT(val) vBIT(val, 16, 16)
1983 #define VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val) vBIT(val, 32, 16)
1984 #define VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val) vBIT(val, 48, 16)
1986 #define VXGE_HAL_LAG_SYS_ID_ADDR(val) vBIT(val, 0, 48)
1990 #define VXGE_HAL_LAG_SYS_CFG_SYS_PRI(val) vBIT(val, 0, 16)
1994 #define VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(val) vBIT(val, 0, 48)
1998 #define VXGE_HAL_LAG_AGGR_ID_CFG_ID(val) vBIT(val, 0, 16)
2000 #define VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY(val) vBIT(val, 0, 16)
2002 #define VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY(val) vBIT(val, 0, 16)
2005 #define VXGE_HAL_LAG_AGGR_OPER_KEY_LAGC_KEY(val) vBIT(val, 0, 16)
2007 #define VXGE_HAL_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val) vBIT(val, 0, 48)
2009 #define VXGE_HAL_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val) vBIT(val, 0, 16)
2010 #define VXGE_HAL_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) vBIT(val, 16, 16)
2024 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val) vBIT(val, 0, 16)
2025 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val) vBIT(val, 16, 16)
2026 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val) vBIT(val, 32, 16)
2027 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val) vBIT(val, 48, 16)
2038 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val) vBIT(val, 0, 48)
2040 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val) vBIT(val, 0, 16)
2041 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val) vBIT(val, 16, 16)
2042 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val) vBIT(val, 32, 16)
2043 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val) vBIT(val, 48, 16)
2054 #define VXGE_HAL_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val) vBIT(val, 0, 16)
2057 #define VXGE_HAL_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val) vBIT(val, 0, 16)
2068 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) vBIT(val, 0, 48)
2070 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) vBIT(val, 0, 16)
2071 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) vBIT(val, 16, 16)
2072 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) vBIT(val, 32, 16)
2073 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) vBIT(val, 48, 16)
2085 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_SELECTED(val) vBIT(val, 6, 2)
2097 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vBIT(val, 37, 3)
2098 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) vBIT(val, 41, 3)
2099 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val) vBIT(val, 44, 4)
2102 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val)\
2103 vBIT(val, 56, 4)
2104 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val)\
2105 vBIT(val, 60, 4)
2107 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_while (val) vBIT(val, 0, 8)
2108 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_while (val) vBIT(val, 8, 8)
2109 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_WAIT_while (val) vBIT(val, 16, 8)
2110 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val) vBIT(val, 24, 8)
2111 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val)\
2112 vBIT(val, 32, 8)
2113 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val)\
2114 vBIT(val, 40, 8)
2115 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val)\
2116 vBIT(val, 48, 8)
2117 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val)\
2118 vBIT(val, 56, 8)
2122 #define VXGE_HAL_TRANSCEIVER_RESET_PORT_TCVR_RESET(val) vBIT(val, 0, 8)
2148 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_SOURCE(val) vBIT(val, 2, 2)
2149 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_SOURCE(val) vBIT(val, 6, 2)
2150 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_SOURCE(val) vBIT(val, 10, 2)
2151 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_SOURCE(val) vBIT(val, 14, 2)
2156 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_EXT_SEL(val) vBIT(val, 32, 4)
2157 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_EXT_SEL(val) vBIT(val, 36, 4)
2158 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_EXT_SEL(val) vBIT(val, 40, 4)
2159 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_EXT_SEL(val) vBIT(val, 44, 4)
2160 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_INT_SEL(val) vBIT(val, 48, 4)
2161 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_INT_SEL(val) vBIT(val, 52, 4)
2162 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_INT_SEL(val) vBIT(val, 56, 4)
2163 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_INT_SEL(val) vBIT(val, 60, 4)
2165 #define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL0(val) vBIT(val, 2, 6)
2166 #define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL1(val) vBIT(val, 10, 6)
2167 #define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL2(val) vBIT(val, 18, 6)
2168 #define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL3(val) vBIT(val, 26, 6)
2174 #define VXGE_HAL_USDC_UGRP_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5)
2176 #define VXGE_HAL_USDC_UGRP_PRIORITY_1_NUMBER_1(val) vBIT(val, 3, 5)
2178 #define VXGE_HAL_USDC_UGRP_PRIORITY_2_NUMBER_2(val) vBIT(val, 3, 5)
2180 #define VXGE_HAL_USDC_UGRP_PRIORITY_3_NUMBER_3(val) vBIT(val, 3, 5)
2182 #define VXGE_HAL_USDC_UGRP_PRIORITY_4_NUMBER_4(val) vBIT(val, 3, 5)
2184 #define VXGE_HAL_USDC_UGRP_PRIORITY_5_NUMBER_5(val) vBIT(val, 3, 5)
2186 #define VXGE_HAL_USDC_UGRP_PRIORITY_6_NUMBER_6(val) vBIT(val, 3, 5)
2188 #define VXGE_HAL_USDC_UGRP_PRIORITY_7_NUMBER_7(val) vBIT(val, 3, 5)
2190 #define VXGE_HAL_USDC_UGRP_PRIORITY_8_NUMBER_8(val) vBIT(val, 3, 5)
2192 #define VXGE_HAL_USDC_UGRP_PRIORITY_9_NUMBER_9(val) vBIT(val, 3, 5)
2194 #define VXGE_HAL_USDC_UGRP_PRIORITY_10_NUMBER_10(val) vBIT(val, 3, 5)
2196 #define VXGE_HAL_USDC_UGRP_PRIORITY_11_NUMBER_11(val) vBIT(val, 3, 5)
2198 #define VXGE_HAL_USDC_UGRP_PRIORITY_12_NUMBER_12(val) vBIT(val, 3, 5)
2200 #define VXGE_HAL_USDC_UGRP_PRIORITY_13_NUMBER_13(val) vBIT(val, 3, 5)
2202 #define VXGE_HAL_USDC_UGRP_PRIORITY_14_NUMBER_14(val) vBIT(val, 3, 5)
2204 #define VXGE_HAL_USDC_UGRP_PRIORITY_15_NUMBER_15(val) vBIT(val, 3, 5)
2206 #define VXGE_HAL_USDC_UGRP_PRIORITY_16_NUMBER_16(val) vBIT(val, 3, 5)
2210 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5)
2211 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_1(val) vBIT(val, 11, 5)
2212 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_2(val) vBIT(val, 19, 5)
2213 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_3(val) vBIT(val, 27, 5)
2214 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_4(val) vBIT(val, 35, 5)
2215 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_5(val) vBIT(val, 43, 5)
2216 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_6(val) vBIT(val, 51, 5)
2217 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_7(val) vBIT(val, 59, 5)
2219 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_8(val) vBIT(val, 3, 5)
2220 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_9(val) vBIT(val, 11, 5)
2221 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_10(val) vBIT(val, 19, 5)
2222 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_11(val) vBIT(val, 27, 5)
2223 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_12(val) vBIT(val, 35, 5)
2224 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_13(val) vBIT(val, 43, 5)
2225 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_14(val) vBIT(val, 51, 5)
2226 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_15(val) vBIT(val, 59, 5)
2228 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_16(val) vBIT(val, 3, 5)
2229 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_17(val) vBIT(val, 11, 5)
2230 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_18(val) vBIT(val, 19, 5)
2231 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_19(val) vBIT(val, 27, 5)
2232 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_20(val) vBIT(val, 35, 5)
2233 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_21(val) vBIT(val, 43, 5)
2234 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_22(val) vBIT(val, 51, 5)
2235 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_23(val) vBIT(val, 59, 5)
2237 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_24(val) vBIT(val, 3, 5)
2238 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_25(val) vBIT(val, 11, 5)
2239 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_26(val) vBIT(val, 19, 5)
2240 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_27(val) vBIT(val, 27, 5)
2241 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_28(val) vBIT(val, 35, 5)
2242 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_29(val) vBIT(val, 43, 5)
2243 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_30(val) vBIT(val, 51, 5)
2244 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_31(val) vBIT(val, 59, 5)
2246 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_32(val) vBIT(val, 3, 5)
2247 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_33(val) vBIT(val, 11, 5)
2248 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_34(val) vBIT(val, 19, 5)
2249 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_35(val) vBIT(val, 27, 5)
2250 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_36(val) vBIT(val, 35, 5)
2251 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_37(val) vBIT(val, 43, 5)
2252 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_38(val) vBIT(val, 51, 5)
2253 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_39(val) vBIT(val, 59, 5)
2255 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_40(val) vBIT(val, 3, 5)
2256 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_41(val) vBIT(val, 11, 5)
2257 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_42(val) vBIT(val, 19, 5)
2258 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_43(val) vBIT(val, 27, 5)
2259 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_44(val) vBIT(val, 35, 5)
2260 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_45(val) vBIT(val, 43, 5)
2261 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_46(val) vBIT(val, 51, 5)
2262 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_47(val) vBIT(val, 59, 5)
2264 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_48(val) vBIT(val, 3, 5)
2265 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_49(val) vBIT(val, 11, 5)
2266 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_50(val) vBIT(val, 19, 5)
2267 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_51(val) vBIT(val, 27, 5)
2268 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_52(val) vBIT(val, 35, 5)
2269 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_53(val) vBIT(val, 43, 5)
2270 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_54(val) vBIT(val, 51, 5)
2271 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_55(val) vBIT(val, 59, 5)
2273 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_56(val) vBIT(val, 3, 5)
2274 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_57(val) vBIT(val, 11, 5)
2275 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_58(val) vBIT(val, 19, 5)
2276 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_59(val) vBIT(val, 27, 5)
2277 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_60(val) vBIT(val, 35, 5)
2278 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_61(val) vBIT(val, 43, 5)
2279 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_62(val) vBIT(val, 51, 5)
2280 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_63(val) vBIT(val, 59, 5)
2282 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_64(val) vBIT(val, 3, 5)
2283 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_65(val) vBIT(val, 11, 5)
2284 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_66(val) vBIT(val, 19, 5)
2285 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_67(val) vBIT(val, 27, 5)
2286 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_68(val) vBIT(val, 35, 5)
2287 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_69(val) vBIT(val, 43, 5)
2288 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_70(val) vBIT(val, 51, 5)
2289 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_71(val) vBIT(val, 59, 5)
2291 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_72(val) vBIT(val, 3, 5)
2292 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_73(val) vBIT(val, 11, 5)
2293 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_74(val) vBIT(val, 19, 5)
2294 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_75(val) vBIT(val, 27, 5)
2295 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_76(val) vBIT(val, 35, 5)
2296 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_77(val) vBIT(val, 43, 5)
2297 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_78(val) vBIT(val, 51, 5)
2298 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_79(val) vBIT(val, 59, 5)
2300 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_80(val) vBIT(val, 3, 5)
2301 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_81(val) vBIT(val, 11, 5)
2302 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_82(val) vBIT(val, 19, 5)
2303 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_83(val) vBIT(val, 27, 5)
2304 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_84(val) vBIT(val, 35, 5)
2305 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_85(val) vBIT(val, 43, 5)
2306 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_86(val) vBIT(val, 51, 5)
2307 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_87(val) vBIT(val, 59, 5)
2309 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_88(val) vBIT(val, 3, 5)
2310 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_89(val) vBIT(val, 11, 5)
2311 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_90(val) vBIT(val, 19, 5)
2312 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_91(val) vBIT(val, 27, 5)
2313 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_92(val) vBIT(val, 35, 5)
2314 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_93(val) vBIT(val, 43, 5)
2315 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_94(val) vBIT(val, 51, 5)
2316 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_95(val) vBIT(val, 59, 5)
2318 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_96(val) vBIT(val, 3, 5)
2319 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_97(val) vBIT(val, 11, 5)
2320 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_98(val) vBIT(val, 19, 5)
2321 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_99(val) vBIT(val, 27, 5)
2322 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_100(val) vBIT(val, 35, 5)
2323 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_101(val) vBIT(val, 43, 5)
2324 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_102(val) vBIT(val, 51, 5)
2325 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_103(val) vBIT(val, 59, 5)
2327 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_104(val) vBIT(val, 3, 5)
2328 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_105(val) vBIT(val, 11, 5)
2329 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_106(val) vBIT(val, 19, 5)
2330 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_107(val) vBIT(val, 27, 5)
2331 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_108(val) vBIT(val, 35, 5)
2332 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_109(val) vBIT(val, 43, 5)
2333 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_110(val) vBIT(val, 51, 5)
2334 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_111(val) vBIT(val, 59, 5)
2336 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_112(val) vBIT(val, 3, 5)
2337 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_113(val) vBIT(val, 11, 5)
2338 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_114(val) vBIT(val, 19, 5)
2339 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_115(val) vBIT(val, 27, 5)
2340 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_116(val) vBIT(val, 35, 5)
2341 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_117(val) vBIT(val, 43, 5)
2342 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_118(val) vBIT(val, 51, 5)
2343 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_119(val) vBIT(val, 59, 5)
2345 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_120(val) vBIT(val, 3, 5)
2346 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_121(val) vBIT(val, 11, 5)
2347 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_122(val) vBIT(val, 19, 5)
2348 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_123(val) vBIT(val, 27, 5)
2349 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_124(val) vBIT(val, 35, 5)
2350 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_125(val) vBIT(val, 43, 5)
2351 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_126(val) vBIT(val, 51, 5)
2352 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_127(val) vBIT(val, 59, 5)
2354 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_128(val) vBIT(val, 3, 5)
2355 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_129(val) vBIT(val, 11, 5)
2356 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_130(val) vBIT(val, 19, 5)
2357 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_131(val) vBIT(val, 27, 5)
2358 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_132(val) vBIT(val, 35, 5)
2359 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_133(val) vBIT(val, 43, 5)
2360 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_134(val) vBIT(val, 51, 5)
2361 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_135(val) vBIT(val, 59, 5)
2363 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_136(val) vBIT(val, 3, 5)
2364 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_137(val) vBIT(val, 11, 5)
2365 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_138(val) vBIT(val, 19, 5)
2366 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_139(val) vBIT(val, 27, 5)
2367 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_140(val) vBIT(val, 35, 5)
2368 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_141(val) vBIT(val, 43, 5)
2369 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_142(val) vBIT(val, 51, 5)
2370 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_143(val) vBIT(val, 59, 5)
2372 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_144(val) vBIT(val, 3, 5)
2373 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_145(val) vBIT(val, 11, 5)
2374 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_146(val) vBIT(val, 19, 5)
2375 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_147(val) vBIT(val, 27, 5)
2376 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_148(val) vBIT(val, 35, 5)
2377 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_149(val) vBIT(val, 43, 5)
2378 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_150(val) vBIT(val, 51, 5)
2379 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_151(val) vBIT(val, 59, 5)
2381 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_19_NUMBER_152(val) vBIT(val, 3, 5)
2383 #define VXGE_HAL_USDC_VPLANE_SGRP_OWN(val) vBIT(val, 0, 32)
2420 #define VXGE_HAL_USDC_CNTRL_MIN_VALUE(val) vBIT(val, 1, 7)
2423 #define VXGE_HAL_USDC_READ_CNTRL_USDC_RDCTRL(val) vBIT(val, 14, 2)
2425 #define VXGE_HAL_USDC_READ_CNTRL_USDC_ADDR(val) vBIT(val, 49, 15)
2427 #define VXGE_HAL_USDC_READ_DATA_READ_DATA(val) vBIT(val, 0, 64)
2431 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5)
2432 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_1(val) vBIT(val, 11, 5)
2433 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_2(val) vBIT(val, 19, 5)
2434 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_3(val) vBIT(val, 27, 5)
2435 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_4(val) vBIT(val, 35, 5)
2436 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_5(val) vBIT(val, 43, 5)
2437 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_6(val) vBIT(val, 51, 5)
2438 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_7(val) vBIT(val, 59, 5)
2440 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_8(val) vBIT(val, 3, 5)
2441 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_9(val) vBIT(val, 11, 5)
2442 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_10(val) vBIT(val, 19, 5)
2443 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_11(val) vBIT(val, 27, 5)
2444 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_12(val) vBIT(val, 35, 5)
2445 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_13(val) vBIT(val, 43, 5)
2446 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_14(val) vBIT(val, 51, 5)
2447 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_15(val) vBIT(val, 59, 5)
2449 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_16(val) vBIT(val, 3, 5)
2450 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_17(val) vBIT(val, 11, 5)
2451 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_18(val) vBIT(val, 19, 5)
2452 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_19(val) vBIT(val, 27, 5)
2453 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_20(val) vBIT(val, 35, 5)
2454 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_21(val) vBIT(val, 43, 5)
2455 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_22(val) vBIT(val, 51, 5)
2456 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_23(val) vBIT(val, 59, 5)
2458 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_24(val) vBIT(val, 3, 5)
2459 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_25(val) vBIT(val, 11, 5)
2460 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_26(val) vBIT(val, 19, 5)
2461 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_27(val) vBIT(val, 27, 5)
2462 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_28(val) vBIT(val, 35, 5)
2463 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_29(val) vBIT(val, 43, 5)
2464 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_30(val) vBIT(val, 51, 5)
2465 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_31(val) vBIT(val, 59, 5)
2467 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_32(val) vBIT(val, 3, 5)
2468 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_33(val) vBIT(val, 11, 5)
2469 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_34(val) vBIT(val, 19, 5)
2470 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_35(val) vBIT(val, 27, 5)
2471 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_36(val) vBIT(val, 35, 5)
2472 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_37(val) vBIT(val, 43, 5)
2473 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_38(val) vBIT(val, 51, 5)
2474 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_39(val) vBIT(val, 59, 5)
2476 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_40(val) vBIT(val, 3, 5)
2477 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_41(val) vBIT(val, 11, 5)
2478 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_42(val) vBIT(val, 19, 5)
2479 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_43(val) vBIT(val, 27, 5)
2480 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_44(val) vBIT(val, 35, 5)
2481 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_45(val) vBIT(val, 43, 5)
2482 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_46(val) vBIT(val, 51, 5)
2483 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_47(val) vBIT(val, 59, 5)
2485 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_48(val) vBIT(val, 3, 5)
2486 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_49(val) vBIT(val, 11, 5)
2487 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_50(val) vBIT(val, 19, 5)
2488 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_51(val) vBIT(val, 27, 5)
2489 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_52(val) vBIT(val, 35, 5)
2490 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_53(val) vBIT(val, 43, 5)
2491 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_54(val) vBIT(val, 51, 5)
2492 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_55(val) vBIT(val, 59, 5)
2494 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_56(val) vBIT(val, 3, 5)
2495 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_57(val) vBIT(val, 11, 5)
2496 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_58(val) vBIT(val, 19, 5)
2497 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_59(val) vBIT(val, 27, 5)
2498 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_60(val) vBIT(val, 35, 5)
2499 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_61(val) vBIT(val, 43, 5)
2500 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_62(val) vBIT(val, 51, 5)
2501 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_63(val) vBIT(val, 59, 5)
2503 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_64(val) vBIT(val, 3, 5)
2504 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_65(val) vBIT(val, 11, 5)
2505 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_66(val) vBIT(val, 19, 5)
2506 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_67(val) vBIT(val, 27, 5)
2507 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_68(val) vBIT(val, 35, 5)
2508 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_69(val) vBIT(val, 43, 5)
2509 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_70(val) vBIT(val, 51, 5)
2510 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_71(val) vBIT(val, 59, 5)
2512 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_72(val) vBIT(val, 3, 5)
2513 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_73(val) vBIT(val, 11, 5)
2514 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_74(val) vBIT(val, 19, 5)
2515 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_75(val) vBIT(val, 27, 5)
2516 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_76(val) vBIT(val, 35, 5)
2517 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_77(val) vBIT(val, 43, 5)
2518 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_78(val) vBIT(val, 51, 5)
2519 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_79(val) vBIT(val, 59, 5)
2521 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_80(val) vBIT(val, 3, 5)
2522 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_81(val) vBIT(val, 11, 5)
2523 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_82(val) vBIT(val, 19, 5)
2524 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_83(val) vBIT(val, 27, 5)
2525 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_84(val) vBIT(val, 35, 5)
2526 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_85(val) vBIT(val, 43, 5)
2527 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_86(val) vBIT(val, 51, 5)
2528 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_87(val) vBIT(val, 59, 5)
2530 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_88(val) vBIT(val, 3, 5)
2531 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_89(val) vBIT(val, 11, 5)
2532 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_90(val) vBIT(val, 19, 5)
2533 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_91(val) vBIT(val, 27, 5)
2534 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_92(val) vBIT(val, 35, 5)
2535 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_93(val) vBIT(val, 43, 5)
2536 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_94(val) vBIT(val, 51, 5)
2537 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_95(val) vBIT(val, 59, 5)
2539 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_96(val) vBIT(val, 3, 5)
2540 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_97(val) vBIT(val, 11, 5)
2541 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_98(val) vBIT(val, 19, 5)
2542 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_99(val) vBIT(val, 27, 5)
2543 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_100(val) vBIT(val, 35, 5)
2544 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_101(val) vBIT(val, 43, 5)
2545 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_102(val) vBIT(val, 51, 5)
2546 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_103(val) vBIT(val, 59, 5)
2548 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_104(val) vBIT(val, 3, 5)
2549 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_105(val) vBIT(val, 11, 5)
2550 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_106(val) vBIT(val, 19, 5)
2551 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_107(val) vBIT(val, 27, 5)
2552 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_108(val) vBIT(val, 35, 5)
2553 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_109(val) vBIT(val, 43, 5)
2554 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_110(val) vBIT(val, 51, 5)
2555 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_111(val) vBIT(val, 59, 5)
2557 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_112(val) vBIT(val, 3, 5)
2558 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_113(val) vBIT(val, 11, 5)
2559 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_114(val) vBIT(val, 19, 5)
2560 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_115(val) vBIT(val, 27, 5)
2561 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_116(val) vBIT(val, 35, 5)
2562 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_117(val) vBIT(val, 43, 5)
2563 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_118(val) vBIT(val, 51, 5)
2564 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_119(val) vBIT(val, 59, 5)
2566 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_120(val) vBIT(val, 3, 5)
2567 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_121(val) vBIT(val, 11, 5)
2568 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_122(val) vBIT(val, 19, 5)
2569 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_123(val) vBIT(val, 27, 5)
2570 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_124(val) vBIT(val, 35, 5)
2571 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_125(val) vBIT(val, 43, 5)
2572 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_126(val) vBIT(val, 51, 5)
2573 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_127(val) vBIT(val, 59, 5)
2575 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_128(val) vBIT(val, 3, 5)
2576 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_129(val) vBIT(val, 11, 5)
2577 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_130(val) vBIT(val, 19, 5)
2578 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_131(val) vBIT(val, 27, 5)
2579 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_132(val) vBIT(val, 35, 5)
2580 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_133(val) vBIT(val, 43, 5)
2581 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_134(val) vBIT(val, 51, 5)
2582 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_135(val) vBIT(val, 59, 5)
2584 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_136(val) vBIT(val, 3, 5)
2585 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_137(val) vBIT(val, 11, 5)
2586 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_138(val) vBIT(val, 19, 5)
2587 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_139(val) vBIT(val, 27, 5)
2588 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_140(val) vBIT(val, 35, 5)
2589 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_141(val) vBIT(val, 43, 5)
2590 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_142(val) vBIT(val, 51, 5)
2591 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_143(val) vBIT(val, 59, 5)
2593 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_144(val) vBIT(val, 3, 5)
2594 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_145(val) vBIT(val, 11, 5)
2595 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_146(val) vBIT(val, 19, 5)
2596 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_147(val) vBIT(val, 27, 5)
2597 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_148(val) vBIT(val, 35, 5)
2598 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_149(val) vBIT(val, 43, 5)
2599 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_150(val) vBIT(val, 51, 5)
2600 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_151(val) vBIT(val, 59, 5)
2602 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_19_NUMBER_152(val) vBIT(val, 3, 5)
2604 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5)
2605 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_1(val) vBIT(val, 11, 5)
2606 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_2(val) vBIT(val, 19, 5)
2607 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_3(val) vBIT(val, 27, 5)
2608 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_4(val) vBIT(val, 35, 5)
2609 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_5(val) vBIT(val, 43, 5)
2610 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_6(val) vBIT(val, 51, 5)
2611 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_7(val) vBIT(val, 59, 5)
2613 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_8(val) vBIT(val, 3, 5)
2614 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_9(val) vBIT(val, 11, 5)
2615 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_10(val) vBIT(val, 19, 5)
2616 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_11(val) vBIT(val, 27, 5)
2617 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_12(val) vBIT(val, 35, 5)
2618 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_13(val) vBIT(val, 43, 5)
2619 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_14(val) vBIT(val, 51, 5)
2620 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_15(val) vBIT(val, 59, 5)
2622 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_16(val) vBIT(val, 3, 5)
2623 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_17(val) vBIT(val, 11, 5)
2624 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_18(val) vBIT(val, 19, 5)
2625 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_19(val) vBIT(val, 27, 5)
2626 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_20(val) vBIT(val, 35, 5)
2627 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_21(val) vBIT(val, 43, 5)
2628 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_22(val) vBIT(val, 51, 5)
2629 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_23(val) vBIT(val, 59, 5)
2631 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_24(val) vBIT(val, 3, 5)
2632 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_25(val) vBIT(val, 11, 5)
2633 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_26(val) vBIT(val, 19, 5)
2634 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_27(val) vBIT(val, 27, 5)
2635 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_28(val) vBIT(val, 35, 5)
2636 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_29(val) vBIT(val, 43, 5)
2637 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_30(val) vBIT(val, 51, 5)
2638 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_31(val) vBIT(val, 59, 5)
2640 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_32(val) vBIT(val, 3, 5)
2641 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_33(val) vBIT(val, 11, 5)
2642 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_34(val) vBIT(val, 19, 5)
2643 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_35(val) vBIT(val, 27, 5)
2644 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_36(val) vBIT(val, 35, 5)
2645 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_37(val) vBIT(val, 43, 5)
2646 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_38(val) vBIT(val, 51, 5)
2647 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_39(val) vBIT(val, 59, 5)
2649 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_40(val) vBIT(val, 3, 5)
2650 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_41(val) vBIT(val, 11, 5)
2651 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_42(val) vBIT(val, 19, 5)
2652 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_43(val) vBIT(val, 27, 5)
2653 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_44(val) vBIT(val, 35, 5)
2654 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_45(val) vBIT(val, 43, 5)
2655 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_46(val) vBIT(val, 51, 5)
2656 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_47(val) vBIT(val, 59, 5)
2658 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_48(val) vBIT(val, 3, 5)
2659 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_49(val) vBIT(val, 11, 5)
2660 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_50(val) vBIT(val, 19, 5)
2661 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_51(val) vBIT(val, 27, 5)
2662 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_52(val) vBIT(val, 35, 5)
2663 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_53(val) vBIT(val, 43, 5)
2664 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_54(val) vBIT(val, 51, 5)
2665 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_55(val) vBIT(val, 59, 5)
2667 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_56(val) vBIT(val, 3, 5)
2668 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_57(val) vBIT(val, 11, 5)
2669 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_58(val) vBIT(val, 19, 5)
2670 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_59(val) vBIT(val, 27, 5)
2671 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_60(val) vBIT(val, 35, 5)
2672 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_61(val) vBIT(val, 43, 5)
2673 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_62(val) vBIT(val, 51, 5)
2674 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_63(val) vBIT(val, 59, 5)
2676 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_64(val) vBIT(val, 3, 5)
2677 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_65(val) vBIT(val, 11, 5)
2678 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_66(val) vBIT(val, 19, 5)
2679 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_67(val) vBIT(val, 27, 5)
2680 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_68(val) vBIT(val, 35, 5)
2681 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_69(val) vBIT(val, 43, 5)
2682 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_70(val) vBIT(val, 51, 5)
2683 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_71(val) vBIT(val, 59, 5)
2685 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_72(val) vBIT(val, 3, 5)
2686 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_73(val) vBIT(val, 11, 5)
2687 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_74(val) vBIT(val, 19, 5)
2688 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_75(val) vBIT(val, 27, 5)
2689 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_76(val) vBIT(val, 35, 5)
2690 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_77(val) vBIT(val, 43, 5)
2691 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_78(val) vBIT(val, 51, 5)
2692 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_79(val) vBIT(val, 59, 5)
2694 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_80(val) vBIT(val, 3, 5)
2695 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_81(val) vBIT(val, 11, 5)
2696 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_82(val) vBIT(val, 19, 5)
2697 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_83(val) vBIT(val, 27, 5)
2698 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_84(val) vBIT(val, 35, 5)
2699 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_85(val) vBIT(val, 43, 5)
2700 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_86(val) vBIT(val, 51, 5)
2701 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_87(val) vBIT(val, 59, 5)
2703 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_88(val) vBIT(val, 3, 5)
2704 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_89(val) vBIT(val, 11, 5)
2705 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_90(val) vBIT(val, 19, 5)
2706 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_91(val) vBIT(val, 27, 5)
2707 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_92(val) vBIT(val, 35, 5)
2708 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_93(val) vBIT(val, 43, 5)
2709 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_94(val) vBIT(val, 51, 5)
2710 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_95(val) vBIT(val, 59, 5)
2712 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_96(val) vBIT(val, 3, 5)
2713 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_97(val) vBIT(val, 11, 5)
2714 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_98(val) vBIT(val, 19, 5)
2715 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_99(val) vBIT(val, 27, 5)
2716 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_100(val) vBIT(val, 35, 5)
2717 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_101(val) vBIT(val, 43, 5)
2718 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_102(val) vBIT(val, 51, 5)
2719 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_103(val) vBIT(val, 59, 5)
2721 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_104(val) vBIT(val, 3, 5)
2722 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_105(val) vBIT(val, 11, 5)
2723 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_106(val) vBIT(val, 19, 5)
2724 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_107(val) vBIT(val, 27, 5)
2725 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_108(val) vBIT(val, 35, 5)
2726 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_109(val) vBIT(val, 43, 5)
2727 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_110(val) vBIT(val, 51, 5)
2728 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_111(val) vBIT(val, 59, 5)
2730 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_112(val) vBIT(val, 3, 5)
2731 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_113(val) vBIT(val, 11, 5)
2732 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_114(val) vBIT(val, 19, 5)
2733 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_115(val) vBIT(val, 27, 5)
2734 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_116(val) vBIT(val, 35, 5)
2735 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_117(val) vBIT(val, 43, 5)
2736 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_118(val) vBIT(val, 51, 5)
2737 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_119(val) vBIT(val, 59, 5)
2739 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_120(val) vBIT(val, 3, 5)
2740 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_121(val) vBIT(val, 11, 5)
2741 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_122(val) vBIT(val, 19, 5)
2742 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_123(val) vBIT(val, 27, 5)
2743 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_124(val) vBIT(val, 35, 5)
2744 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_125(val) vBIT(val, 43, 5)
2745 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_126(val) vBIT(val, 51, 5)
2746 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_127(val) vBIT(val, 59, 5)
2748 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_128(val) vBIT(val, 3, 5)
2749 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_129(val) vBIT(val, 11, 5)
2750 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_130(val) vBIT(val, 19, 5)
2751 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_131(val) vBIT(val, 27, 5)
2752 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_132(val) vBIT(val, 35, 5)
2753 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_133(val) vBIT(val, 43, 5)
2754 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_134(val) vBIT(val, 51, 5)
2755 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_135(val) vBIT(val, 59, 5)
2757 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_136(val) vBIT(val, 3, 5)
2758 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_137(val) vBIT(val, 11, 5)
2759 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_138(val) vBIT(val, 19, 5)
2760 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_139(val) vBIT(val, 27, 5)
2761 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_140(val) vBIT(val, 35, 5)
2762 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_141(val) vBIT(val, 43, 5)
2763 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_142(val) vBIT(val, 51, 5)
2764 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_143(val) vBIT(val, 59, 5)
2766 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_144(val) vBIT(val, 3, 5)
2767 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_145(val) vBIT(val, 11, 5)
2768 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_146(val) vBIT(val, 19, 5)
2769 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_147(val) vBIT(val, 27, 5)
2770 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_148(val) vBIT(val, 35, 5)
2771 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_149(val) vBIT(val, 43, 5)
2772 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_150(val) vBIT(val, 51, 5)
2773 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_151(val) vBIT(val, 59, 5)
2775 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_19_NUMBER_152(val) vBIT(val, 3, 5)
2820 #define VXGE_HAL_PDA_PDA_CONTROL_0_PCC_MAX(val) vBIT(val, 4, 4)
2821 #define VXGE_HAL_PDA_PDA_CONTROL_0_FE_MAX(val) vBIT(val, 13, 3)
2823 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_0(val) vBIT(val, 5, 3)
2824 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_1(val) vBIT(val, 13, 3)
2825 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_2(val) vBIT(val, 21, 3)
2826 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_3(val) vBIT(val, 29, 3)
2827 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_4(val) vBIT(val, 37, 3)
2828 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_5(val) vBIT(val, 45, 3)
2829 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_6(val) vBIT(val, 53, 3)
2830 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_7(val) vBIT(val, 61, 3)
2832 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_8(val) vBIT(val, 5, 3)
2833 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_9(val) vBIT(val, 13, 3)
2834 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_10(val) vBIT(val, 21, 3)
2835 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_11(val) vBIT(val, 29, 3)
2836 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_12(val) vBIT(val, 37, 3)
2837 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_13(val) vBIT(val, 45, 3)
2838 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_14(val) vBIT(val, 53, 3)
2839 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_15(val) vBIT(val, 61, 3)
2841 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_16(val) vBIT(val, 5, 3)
2842 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_17(val) vBIT(val, 13, 3)
2843 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_18(val) vBIT(val, 21, 3)
2844 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_19(val) vBIT(val, 29, 3)
2845 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_20(val) vBIT(val, 37, 3)
2847 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_CXP(val) vBIT(val, 5, 3)
2848 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_H2L(val) vBIT(val, 13, 3)
2849 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_KDFC(val) vBIT(val, 21, 3)
2850 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_MP(val) vBIT(val, 29, 3)
2851 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_PE(val) vBIT(val, 37, 3)
2852 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_QCC(val) vBIT(val, 45, 3)
2863 #define VXGE_HAL_PCC_CONTROL_FE_ENABLE(val) vBIT(val, 6, 2)
2867 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_0_CTR(val) vBIT(val, 4, 4)
2868 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_1_CTR(val) vBIT(val, 12, 4)
2869 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_2_CTR(val) vBIT(val, 20, 4)
2870 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_3_CTR(val) vBIT(val, 28, 4)
2871 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_4_CTR(val) vBIT(val, 36, 4)
2872 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_5_CTR(val) vBIT(val, 44, 4)
2873 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_6_CTR(val) vBIT(val, 52, 4)
2874 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_7_CTR(val) vBIT(val, 60, 4)
2876 #define VXGE_HAL_RTDMA_BW_TIMER_TIMER_CTRL(val) vBIT(val, 12, 4)
2893 #define VXGE_HAL_G3CMCT_CONFIG0_RD_CMD_LATENCY_RPATH(val) vBIT(val, 5, 3)
2894 #define VXGE_HAL_G3CMCT_CONFIG0_RD_CMD_LATENCY(val) vBIT(val, 13, 3)
2895 #define VXGE_HAL_G3CMCT_CONFIG0_REFRESH_PER(val) vBIT(val, 16, 16)
2896 #define VXGE_HAL_G3CMCT_CONFIG0_TRC(val) vBIT(val, 35, 5)
2897 #define VXGE_HAL_G3CMCT_CONFIG0_TRRD(val) vBIT(val, 44, 4)
2898 #define VXGE_HAL_G3CMCT_CONFIG0_TFAW(val) vBIT(val, 50, 6)
2899 #define VXGE_HAL_G3CMCT_CONFIG0_RD_FIFO_THR(val) vBIT(val, 58, 6)
2901 #define VXGE_HAL_G3CMCT_CONFIG1_BIC_THR(val) vBIT(val, 3, 5)
2904 #define VXGE_HAL_G3CMCT_CONFIG1_RD_SAMPLING(val) vBIT(val, 29, 3)
2906 #define VXGE_HAL_G3CMCT_CONFIG1_BIC_HI_THR(val) vBIT(val, 43, 5)
2907 #define VXGE_HAL_G3CMCT_CONFIG1_BIC_MODE(val) vBIT(val, 54, 2)
2908 #define VXGE_HAL_G3CMCT_CONFIG1_ECC_ENABLE(val) vBIT(val, 57, 7)
2910 #define VXGE_HAL_G3CMCT_CONFIG2_DEV_USE_ENABLE(val) vBIT(val, 6, 2)
2911 #define VXGE_HAL_G3CMCT_CONFIG2_DEV_USE_VALUE(val) vBIT(val, 9, 7)
2912 #define VXGE_HAL_G3CMCT_CONFIG2_ARBITER_CTRL(val) vBIT(val, 22, 2)
2915 #define VXGE_HAL_G3CMCT_CONFIG2_LAST_CADD(val) vBIT(val, 43, 13)
2917 #define VXGE_HAL_G3CMCT_INIT0_MRS_BAD(val) vBIT(val, 5, 3)
2918 #define VXGE_HAL_G3CMCT_INIT0_MRS_WL(val) vBIT(val, 13, 3)
2921 #define VXGE_HAL_G3CMCT_INIT0_MRS_CL(val) vBIT(val, 44, 4)
2923 #define VXGE_HAL_G3CMCT_INIT0_MRS_BL(val) vBIT(val, 62, 2)
2925 #define VXGE_HAL_G3CMCT_INIT1_EMRS_BAD(val) vBIT(val, 5, 3)
2930 #define VXGE_HAL_G3CMCT_INIT1_EMRS_TWR(val) vBIT(val, 53, 3)
2931 #define VXGE_HAL_G3CMCT_INIT1_EMRS_DQ_TER(val) vBIT(val, 62, 2)
2933 #define VXGE_HAL_G3CMCT_INIT2_EMRS_DR_STR(val) vBIT(val, 6, 2)
2935 #define VXGE_HAL_G3CMCT_INIT2_POWER_UP_DELAY(val) vBIT(val, 16, 24)
2936 #define VXGE_HAL_G3CMCT_INIT2_ACTIVE_CMD_DELAY(val) vBIT(val, 40, 24)
2938 #define VXGE_HAL_G3CMCT_INIT3_TRP_DELAY(val) vBIT(val, 0, 8)
2939 #define VXGE_HAL_G3CMCT_INIT3_TMRD_DELAY(val) vBIT(val, 8, 8)
2940 #define VXGE_HAL_G3CMCT_INIT3_TWR2PRE_DELAY(val) vBIT(val, 16, 8)
2941 #define VXGE_HAL_G3CMCT_INIT3_TRD2PRE_DELAY(val) vBIT(val, 24, 8)
2942 #define VXGE_HAL_G3CMCT_INIT3_TRCDR_DELAY(val) vBIT(val, 32, 8)
2943 #define VXGE_HAL_G3CMCT_INIT3_TRCDW_DELAY(val) vBIT(val, 40, 8)
2944 #define VXGE_HAL_G3CMCT_INIT3_TWR2RD_DELAY(val) vBIT(val, 48, 8)
2945 #define VXGE_HAL_G3CMCT_INIT3_TRD2WR_DELAY(val) vBIT(val, 56, 8)
2947 #define VXGE_HAL_G3CMCT_INIT4_TRFC_DELAY(val) vBIT(val, 0, 8)
2948 #define VXGE_HAL_G3CMCT_INIT4_REFRESH_BURSTS(val) vBIT(val, 12, 4)
2950 #define VXGE_HAL_G3CMCT_INIT4_VENDOR_ID(val) vBIT(val, 32, 8)
2951 #define VXGE_HAL_G3CMCT_INIT4_OOO_DEPTH(val) vBIT(val, 42, 6)
2955 #define VXGE_HAL_G3CMCT_INIT5_TRAS_DELAY(val) vBIT(val, 3, 5)
2956 #define VXGE_HAL_G3CMCT_INIT5_TVID_DELAY(val) vBIT(val, 8, 8)
2957 #define VXGE_HAL_G3CMCT_INIT5_TWR_APRE2CMD(val) vBIT(val, 16, 8)
2958 #define VXGE_HAL_G3CMCT_INIT5_TRD_APRE2CMD(val) vBIT(val, 24, 8)
2959 #define VXGE_HAL_G3CMCT_INIT5_TWR_APRE2CMD_CON(val) vBIT(val, 32, 8)
2960 #define VXGE_HAL_G3CMCT_INIT5_GDDR3_DLL_DELAY(val) vBIT(val, 40, 24)
2962 #define VXGE_HAL_G3CMCT_DLL_TRAINING1_DLL_TRA_DATA00(val) vBIT(val, 0, 64)
2964 #define VXGE_HAL_G3CMCT_DLL_TRAINING2_DLL_TRA_DATA01(val) vBIT(val, 0, 64)
2966 #define VXGE_HAL_G3CMCT_DLL_TRAINING3_DLL_TRA_DATA10(val) vBIT(val, 0, 64)
2968 #define VXGE_HAL_G3CMCT_DLL_TRAINING4_DLL_TRA_DATA11(val) vBIT(val, 0, 64)
2970 #define VXGE_HAL_G3CMCT_DLL_TRAINING6_DLL_TRA_DATA20(val) vBIT(val, 0, 64)
2972 #define VXGE_HAL_G3CMCT_DLL_TRAINING7_DLL_TRA_DATA21(val) vBIT(val, 0, 64)
2974 #define VXGE_HAL_G3CMCT_DLL_TRAINING8_DLL_TRA_DATA30(val) vBIT(val, 0, 64)
2976 #define VXGE_HAL_G3CMCT_DLL_TRAINING9_DLL_TRA_DATA31(val) vBIT(val, 0, 64)
2978 #define VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_RADD(val) vBIT(val, 2, 14)
2979 #define VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_CADD0(val) vBIT(val, 21, 11)
2980 #define VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_CADD1(val) vBIT(val, 37, 11)
2982 #define VXGE_HAL_G3CMCT_DLL_TRAINING10_DLL_TP_READS(val) vBIT(val, 4, 4)
2983 #define VXGE_HAL_G3CMCT_DLL_TRAINING10_DLL_SAMPLES(val) vBIT(val, 8, 8)
2984 #define VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_LOOPS(val) vBIT(val, 18, 14)
2985 #define VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_PASS_CNT(val) vBIT(val, 33, 7)
2986 #define VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_STEP(val) vBIT(val, 41, 7)
2988 #define VXGE_HAL_G3CMCT_DLL_TRAINING11_ICTRL_DLL_TRA_CNT(val) vBIT(val, 0, 48)
2989 #define VXGE_HAL_G3CMCT_DLL_TRAINING11_ICTRL_DLL_TRA_DIS(val) vBIT(val, 54, 2)
2991 #define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2RD_DELAY(val) vBIT(val, 4, 4)
2992 #define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2WR_DELAY(val) vBIT(val, 12, 4)
2993 #define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2PRE_DELAY(val) vBIT(val, 20, 4)
2994 #define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2ACT_DELAY(val) vBIT(val, 28, 4)
2995 #define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2RD_DELAY(val) vBIT(val, 36, 4)
2996 #define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2WR_DELAY(val) vBIT(val, 44, 4)
2997 #define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2PRE_DELAY(val) vBIT(val, 52, 4)
2998 #define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2ACT_DELAY(val) vBIT(val, 60, 4)
3000 #define VXGE_HAL_G3CMCT_TEST0_TEST_START_RADD(val) vBIT(val, 2, 14)
3001 #define VXGE_HAL_G3CMCT_TEST0_TEST_END_RADD(val) vBIT(val, 18, 14)
3002 #define VXGE_HAL_G3CMCT_TEST0_TEST_START_CADD(val) vBIT(val, 37, 11)
3003 #define VXGE_HAL_G3CMCT_TEST0_TEST_END_CADD(val) vBIT(val, 53, 11)
3005 #define VXGE_HAL_G3CMCT_TEST01_TEST_BANK(val) vBIT(val, 0, 8)
3006 #define VXGE_HAL_G3CMCT_TEST01_TEST_CTRL(val) vBIT(val, 12, 4)
3010 #define VXGE_HAL_G3CMCT_TEST01_ECC_DEC_TEST_FAIL_CNTR(val) vBIT(val, 40, 16)
3013 #define VXGE_HAL_G3CMCT_TEST1_TX_TEST_DATA(val) vBIT(val, 0, 64)
3015 #define VXGE_HAL_G3CMCT_TEST2_TX_TEST_DATA(val) vBIT(val, 0, 64)
3017 #define VXGE_HAL_G3CMCT_TEST11_TX_TEST_DATA1(val) vBIT(val, 0, 64)
3019 #define VXGE_HAL_G3CMCT_TEST21_TX_TEST_DATA1(val) vBIT(val, 0, 64)
3021 #define VXGE_HAL_G3CMCT_TEST3_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64)
3023 #define VXGE_HAL_G3CMCT_TEST4_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64)
3025 #define VXGE_HAL_G3CMCT_TEST31_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64)
3027 #define VXGE_HAL_G3CMCT_TEST41_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64)
3029 #define VXGE_HAL_G3CMCT_TEST5_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64)
3031 #define VXGE_HAL_G3CMCT_TEST6_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64)
3033 #define VXGE_HAL_G3CMCT_TEST51_ECC_DEC_RX_FAILED_TEST_DATA1(val)\
3034 vBIT(val, 0, 64)
3036 #define VXGE_HAL_G3CMCT_TEST61_ECC_DEC_RX_FAILED_TEST_DATA1(val)\
3037 vBIT(val, 0, 64)
3039 #define VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_RADD(val) vBIT(val, 0, 14)
3040 #define VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_CADD(val) vBIT(val, 19, 11)
3041 #define VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_BANK(val) vBIT(val, 32, 8)
3043 #define VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_RADD1(val) vBIT(val, 0, 14)
3044 #define VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_CADD1(val) vBIT(val, 19, 11)
3045 #define VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_BANK1(val) vBIT(val, 32, 8)
3047 #define VXGE_HAL_G3CMCT_INIT41_VENDOR_ID_U(val) vBIT(val, 0, 8)
3050 #define VXGE_HAL_G3CMCT_TEST8_ECC_DEC_U_RX_TEST_DATA_U(val) vBIT(val, 0, 64)
3052 #define VXGE_HAL_G3CMCT_TEST9_ECC_DEC_U_RX_TEST_DATA_U(val) vBIT(val, 0, 64)
3054 #define VXGE_HAL_G3CMCT_TEST10_ECC_DEC_U_RX_TEST_DATA1_U(val) vBIT(val, 0, 64)
3056 #define VXGE_HAL_G3CMCT_TEST101_ECC_DEC_U_RX_TEST_DATA1_U(val) vBIT(val, 0, 64)
3058 #define VXGE_HAL_G3CMCT_TEST12_ECC_DEC_U_RX_FAILED_TEST_DATA_U(val)\
3059 vBIT(val, 0, 64)
3061 #define VXGE_HAL_G3CMCT_TEST13_ECC_DEC_U_RX_FAILED_TEST_DATA_U(val)\
3062 vBIT(val, 0, 64)
3064 #define VXGE_HAL_G3CMCT_TEST14_ECC_DEC_U_RX_FAILED_TEST_DATA1_U(val)\
3065 vBIT(val, 0, 64)
3067 #define VXGE_HAL_G3CMCT_TEST15_ECC_DEC_U_RX_FAILED_TEST_DATA1_U(val)\
3068 vBIT(val, 0, 64)
3070 #define VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_RADD_U(val)\
3071 vBIT(val, 0, 14)
3072 #define VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_CADD_U(val)\
3073 vBIT(val, 19, 11)
3074 #define VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_BANK_U(val)\
3075 vBIT(val, 32, 8)
3077 #define VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_RADD1_U(val)\
3078 vBIT(val, 0, 14)
3079 #define VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_CADD1_U(val)\
3080 vBIT(val, 19, 11)
3081 #define VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_BANK1_U(val)\
3082 vBIT(val, 32, 8)
3084 #define VXGE_HAL_G3CMCT_TEST18_ECC_DEC_U_TEST_FAIL_CNTR_U(val)\
3085 vBIT(val, 0, 16)
3087 #define VXGE_HAL_G3CMCT_LOOP_BACK_TDATA(val) vBIT(val, 0, 32)
3091 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_IDLE_VAL(val) vBIT(val, 56, 8)
3093 #define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_START_VAL(val) vBIT(val, 1, 7)
3094 #define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_END_VAL(val) vBIT(val, 9, 7)
3095 #define VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_IDLE_VAL(val) vBIT(val, 16, 8)
3096 #define VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_START_VAL(val) vBIT(val, 25, 7)
3097 #define VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_END_VAL(val) vBIT(val, 33, 7)
3098 #define VXGE_HAL_G3CMCT_LOOP_BACK1_STEPS(val) vBIT(val, 45, 3)
3099 #define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_MIN_FILTER(val) vBIT(val, 49, 7)
3100 #define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_MAX_FILTER(val) vBIT(val, 57, 7)
3102 #define VXGE_HAL_G3CMCT_LOOP_BACK2_WDLL_MIN_FILTER(val) vBIT(val, 1, 7)
3103 #define VXGE_HAL_G3CMCT_LOOP_BACK2_WDLL_MAX_FILTER(val) vBIT(val, 9, 7)
3105 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_RDLL_RESULT(val) vBIT(val, 0, 8)
3106 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_WDLL_RESULT(val) vBIT(val, 8, 8)
3107 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_RDLL_RESULT(val) vBIT(val, 16, 8)
3108 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_WDLL_RESULT(val) vBIT(val, 24, 8)
3109 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_RDLL_MON_RESULT(val)\
3110 vBIT(val, 32, 8)
3111 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_RDLL_MON_RESULT(val)\
3112 vBIT(val, 40, 8)
3114 #define VXGE_HAL_G3CMCT_LOOP_BACK4_LBCTRL_IO_U_PASS_FAILN(val) vBIT(val, 0, 32)
3115 #define VXGE_HAL_G3CMCT_LOOP_BACK4_LBCTRL_IO_L_PASS_FAILN(val) vBIT(val, 32, 32)
3117 #define VXGE_HAL_G3CMCT_LOOP_BACK5_RDLL_START_IO_VAL(val) vBIT(val, 1, 7)
3118 #define VXGE_HAL_G3CMCT_LOOP_BACK5_RDLL_END_IO_VAL(val) vBIT(val, 9, 7)
3122 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_U_MIN_VAL(val) vBIT(val, 1, 7)
3123 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_U_MAX_VAL(val) vBIT(val, 9, 7)
3124 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_L_MIN_VAL(val) vBIT(val, 17, 7)
3125 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_L_MAX_VAL(val) vBIT(val, 25, 7)
3126 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_U_MIN_VAL(val)\
3127 vBIT(val, 33, 7)
3128 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_U_MAX_VAL(val)\
3129 vBIT(val, 41, 7)
3130 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_L_MIN_VAL(val)\
3131 vBIT(val, 49, 7)
3132 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_L_MAX_VAL(val)\
3133 vBIT(val, 57, 7)
3135 #define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_U_MIN_VAL(val) vBIT(val, 1, 7)
3136 #define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_U_MAX_VAL(val) vBIT(val, 9, 7)
3137 #define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_L_MIN_VAL(val) vBIT(val, 17, 7)
3138 #define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_L_MAX_VAL(val) vBIT(val, 25, 7)
3140 #define VXGE_HAL_G3CMCT_TRAN_WRD_CNT_CTRL_PIPE_WR(val) vBIT(val, 0, 32)
3141 #define VXGE_HAL_G3CMCT_TRAN_WRD_CNT_CTRL_PIPE_RD(val) vBIT(val, 32, 32)
3143 #define VXGE_HAL_G3CMCT_TRAN_AP_CNT_CTRL_PIPE_ACT(val) vBIT(val, 0, 16)
3144 #define VXGE_HAL_G3CMCT_TRAN_AP_CNT_CTRL_PIPE_PRE(val) vBIT(val, 16, 16)
3149 #define VXGE_HAL_G3CMCT_G3BIST_BTCTRL_STATUS_MAIN(val) vBIT(val, 21, 3)
3150 #define VXGE_HAL_G3CMCT_G3BIST_BTCTRL_STATUS_ICTRL(val) vBIT(val, 29, 3)
3181 #define VXGE_HAL_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val) vBIT(val, 0, 8)
3182 #define VXGE_HAL_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vBIT(val, 8, 8)
3183 #define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_0(val) vBIT(val, 16, 8)
3184 #define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_1(val) vBIT(val, 24, 8)
3185 #define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_2(val) vBIT(val, 32, 8)
3186 #define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_3(val) vBIT(val, 40, 8)
3190 #define VXGE_HAL_DBG_REG1_0_INCTRL_QUEUE0_RX_NON_OFFLOAD_FRM_CNT(val)\
3191 vBIT(val, 0, 16)
3192 #define VXGE_HAL_DBG_REG1_0_INCTRL_QUEUE0_RX_OFFLOAD_FRM_CNT(val)\
3193 vBIT(val, 16, 16)
3194 #define VXGE_HAL_DBG_REG1_0_RP_QUEUE0_NON_OFFLOAD_XMFD_CNT(val)\
3195 vBIT(val, 32, 16)
3196 #define VXGE_HAL_DBG_REG1_0_RP_QUEUE0_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
3198 #define VXGE_HAL_DBG_REG1_1_INCTRL_QUEUE1_RX_NON_OFFLOAD_FRM_CNT(val)\
3199 vBIT(val, 0, 16)
3200 #define VXGE_HAL_DBG_REG1_1_INCTRL_QUEUE1_RX_OFFLOAD_FRM_CNT(val)\
3201 vBIT(val, 16, 16)
3202 #define VXGE_HAL_DBG_REG1_1_RP_QUEUE1_NON_OFFLOAD_XMFD_CNT(val)\
3203 vBIT(val, 32, 16)
3204 #define VXGE_HAL_DBG_REG1_1_RP_QUEUE1_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
3206 #define VXGE_HAL_DBG_REG1_2_INCTRL_QUEUE2_RX_NON_OFFLOAD_FRM_CNT(val)\
3207 vBIT(val, 0, 16)
3208 #define VXGE_HAL_DBG_REG1_2_INCTRL_QUEUE2_RX_OFFLOAD_FRM_CNT(val)\
3209 vBIT(val, 16, 16)
3210 #define VXGE_HAL_DBG_REG1_2_RP_QUEUE2_NON_OFFLOAD_XMFD_CNT(val)\
3211 vBIT(val, 32, 16)
3212 #define VXGE_HAL_DBG_REG1_2_RP_QUEUE2_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
3214 #define VXGE_HAL_DBG_REG1_3_INCTRL_QUEUE3_RX_NON_OFFLOAD_FRM_CNT(val)\
3215 vBIT(val, 0, 16)
3216 #define VXGE_HAL_DBG_REG1_3_INCTRL_QUEUE3_RX_OFFLOAD_FRM_CNT(val)\
3217 vBIT(val, 16, 16)
3218 #define VXGE_HAL_DBG_REG1_3_RP_QUEUE3_NON_OFFLOAD_XMFD_CNT(val)\
3219 vBIT(val, 32, 16)
3220 #define VXGE_HAL_DBG_REG1_3_RP_QUEUE3_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
3222 #define VXGE_HAL_DBG_REG1_4_INCTRL_QUEUE4_RX_NON_OFFLOAD_FRM_CNT(val)\
3223 vBIT(val, 0, 16)
3224 #define VXGE_HAL_DBG_REG1_4_INCTRL_QUEUE4_RX_OFFLOAD_FRM_CNT(val)\
3225 vBIT(val, 16, 16)
3226 #define VXGE_HAL_DBG_REG1_4_RP_QUEUE4_NON_OFFLOAD_XMFD_CNT(val)\
3227 vBIT(val, 32, 16)
3228 #define VXGE_HAL_DBG_REG1_4_RP_QUEUE4_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
3230 #define VXGE_HAL_DBG_REG1_5_INCTRL_QUEUE5_RX_NON_OFFLOAD_FRM_CNT(val)\
3231 vBIT(val, 0, 16)
3232 #define VXGE_HAL_DBG_REG1_5_INCTRL_QUEUE5_RX_OFFLOAD_FRM_CNT(val)\
3233 vBIT(val, 16, 16)
3234 #define VXGE_HAL_DBG_REG1_5_RP_QUEUE5_NON_OFFLOAD_XMFD_CNT(val)\
3235 vBIT(val, 32, 16)
3236 #define VXGE_HAL_DBG_REG1_5_RP_QUEUE5_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
3238 #define VXGE_HAL_DBG_REG1_6_INCTRL_QUEUE6_RX_NON_OFFLOAD_FRM_CNT(val)\
3239 vBIT(val, 0, 16)
3240 #define VXGE_HAL_DBG_REG1_6_INCTRL_QUEUE6_RX_OFFLOAD_FRM_CNT(val)\
3241 vBIT(val, 16, 16)
3242 #define VXGE_HAL_DBG_REG1_6_RP_QUEUE6_NON_OFFLOAD_XMFD_CNT(val)\
3243 vBIT(val, 32, 16)
3244 #define VXGE_HAL_DBG_REG1_6_RP_QUEUE6_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
3246 #define VXGE_HAL_DBG_REG1_7_INCTRL_QUEUE7_RX_NON_OFFLOAD_FRM_CNT(val)\
3247 vBIT(val, 0, 16)
3248 #define VXGE_HAL_DBG_REG1_7_INCTRL_QUEUE7_RX_OFFLOAD_FRM_CNT(val)\
3249 vBIT(val, 16, 16)
3250 #define VXGE_HAL_DBG_REG1_7_RP_QUEUE7_NON_OFFLOAD_XMFD_CNT(val)\
3251 vBIT(val, 32, 16)
3252 #define VXGE_HAL_DBG_REG1_7_RP_QUEUE7_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
3254 #define VXGE_HAL_DBG_REG2_XFMDCNT_XFMD_AVAILABLE(val) vBIT(val, 6, 18)
3255 #define VXGE_HAL_DBG_REG2_RP_FBMC_PTM_DATA_PHASES(val) vBIT(val, 24, 32)
3257 #define VXGE_HAL_DBG_REG3_XFMD_ADV_FBMC_RQA_QUEUE_STROBES(val) vBIT(val, 0, 16)
3258 #define VXGE_HAL_DBG_REG3_XFMD_ADV_FBMC_RQA_MC_STROBES(val) vBIT(val, 16, 16)
3259 #define VXGE_HAL_DBG_REG3_XFMD_ADV_RQA_FBMC_QUEUE_SELECT(val) vBIT(val, 32, 16)
3260 #define VXGE_HAL_DBG_REG3_XFMD_ADV_RQA_FBMC_MC_SELECT(val) vBIT(val, 48, 16)
3262 #define VXGE_HAL_DBG_REG4_RP_FBMC_ONE_HEADERS(val) vBIT(val, 0, 16)
3264 #define VXGE_HAL_DBG_REG5_INCTRL_TOTAL_ING_FRMS(val) vBIT(val, 0, 32)
3265 #define VXGE_HAL_DBG_REG5_RP_TOTAL_EGR_FRMS(val) vBIT(val, 32, 32)
3270 #define VXGE_HAL_RX_QUEUE_CFG_INGRESS_FIFO_THR(val) vBIT(val, 60, 4)
3272 #define VXGE_HAL_RX_QUEUE_SIZE_Q_SIZE(val) vBIT(val, 0, 24)
3273 #define VXGE_HAL_RX_QUEUE_SIZE_Q_LAST_ADD(val) vBIT(val, 24, 24)
3275 #define VXGE_HAL_RX_QUEUE_SIZE_Q15_SIZE(val) vBIT(val, 0, 24)
3276 #define VXGE_HAL_RX_QUEUE_SIZE_Q15_LAST_ADD(val) vBIT(val, 24, 24)
3278 #define VXGE_HAL_RX_QUEUE_SIZE_Q16_SIZE(val) vBIT(val, 0, 24)
3279 #define VXGE_HAL_RX_QUEUE_SIZE_Q16_LAST_ADD(val) vBIT(val, 24, 24)
3281 #define VXGE_HAL_RX_QUEUE_SIZE_Q17_SIZE(val) vBIT(val, 0, 24)
3282 #define VXGE_HAL_RX_QUEUE_SIZE_Q17_LAST_ADD(val) vBIT(val, 24, 24)
3286 #define VXGE_HAL_RX_QUEUE_START_Q0_QUEUE_BANKS(val) vBIT(val, 6, 2)
3287 #define VXGE_HAL_RX_QUEUE_START_Q0_SBANK(val) vBIT(val, 13, 3)
3288 #define VXGE_HAL_RX_QUEUE_START_Q0_SROW(val) vBIT(val, 18, 14)
3289 #define VXGE_HAL_RX_QUEUE_START_Q0_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3290 #define VXGE_HAL_RX_QUEUE_START_Q0_FDP_NONOFFLOAD_OUTST_FRMS(val)\
3291 vBIT(val, 55, 9)
3293 #define VXGE_HAL_RX_QUEUE_START_Q1_QUEUE_BANKS(val) vBIT(val, 6, 2)
3294 #define VXGE_HAL_RX_QUEUE_START_Q1_SBANK(val) vBIT(val, 13, 3)
3295 #define VXGE_HAL_RX_QUEUE_START_Q1_SROW(val) vBIT(val, 18, 14)
3296 #define VXGE_HAL_RX_QUEUE_START_Q1_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3297 #define VXGE_HAL_RX_QUEUE_START_Q1_FDP_NONOFFLOAD_OUTST_FRMS(val)\
3298 vBIT(val, 55, 9)
3300 #define VXGE_HAL_RX_QUEUE_START_Q2_QUEUE_BANKS(val) vBIT(val, 6, 2)
3301 #define VXGE_HAL_RX_QUEUE_START_Q2_SBANK(val) vBIT(val, 13, 3)
3302 #define VXGE_HAL_RX_QUEUE_START_Q2_SROW(val) vBIT(val, 18, 14)
3303 #define VXGE_HAL_RX_QUEUE_START_Q2_FDP_OFFLOAD_OUTST_FRMS(val)\
3304 vBIT(val, 39, 9)
3305 #define VXGE_HAL_RX_QUEUE_START_Q2_FDP_NONOFFLOAD_OUTST_FRMS(val)\
3306 vBIT(val, 55, 9)
3308 #define VXGE_HAL_RX_QUEUE_START_Q3_QUEUE_BANKS(val) vBIT(val, 6, 2)
3309 #define VXGE_HAL_RX_QUEUE_START_Q3_SBANK(val) vBIT(val, 13, 3)
3310 #define VXGE_HAL_RX_QUEUE_START_Q3_SROW(val) vBIT(val, 18, 14)
3311 #define VXGE_HAL_RX_QUEUE_START_Q3_FDP_OFFLOAD_OUTST_FRMS(val)\
3312 vBIT(val, 39, 9)
3313 #define VXGE_HAL_RX_QUEUE_START_Q3_FDP_NONOFFLOAD_OUTST_FRMS(val)\
3314 vBIT(val, 55, 9)
3316 #define VXGE_HAL_RX_QUEUE_START_Q4_QUEUE_BANKS(val) vBIT(val, 6, 2)
3317 #define VXGE_HAL_RX_QUEUE_START_Q4_SBANK(val) vBIT(val, 13, 3)
3318 #define VXGE_HAL_RX_QUEUE_START_Q4_SROW(val) vBIT(val, 18, 14)
3319 #define VXGE_HAL_RX_QUEUE_START_Q4_FDP_OFFLOAD_OUTST_FRMS(val)\
3320 vBIT(val, 39, 9)
3321 #define VXGE_HAL_RX_QUEUE_START_Q4_FDP_NONOFFLOAD_OUTST_FRMS(val)\
3322 vBIT(val, 55, 9)
3324 #define VXGE_HAL_RX_QUEUE_START_Q5_QUEUE_BANKS(val) vBIT(val, 6, 2)
3325 #define VXGE_HAL_RX_QUEUE_START_Q5_SBANK(val) vBIT(val, 13, 3)
3326 #define VXGE_HAL_RX_QUEUE_START_Q5_SROW(val) vBIT(val, 18, 14)
3327 #define VXGE_HAL_RX_QUEUE_START_Q5_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3328 #define VXGE_HAL_RX_QUEUE_START_Q5_FDP_NONOFFLOAD_OUTST_FRMS(val)\
3329 vBIT(val, 55, 9)
3331 #define VXGE_HAL_RX_QUEUE_START_Q6_QUEUE_BANKS(val) vBIT(val, 6, 2)
3332 #define VXGE_HAL_RX_QUEUE_START_Q6_SBANK(val) vBIT(val, 13, 3)
3333 #define VXGE_HAL_RX_QUEUE_START_Q6_SROW(val) vBIT(val, 18, 14)
3334 #define VXGE_HAL_RX_QUEUE_START_Q6_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3335 #define VXGE_HAL_RX_QUEUE_START_Q6_FDP_NONOFFLOAD_OUTST_FRMS(val)\
3336 vBIT(val, 55, 9)
3338 #define VXGE_HAL_RX_QUEUE_START_Q7_QUEUE_BANKS(val) vBIT(val, 6, 2)
3339 #define VXGE_HAL_RX_QUEUE_START_Q7_SBANK(val) vBIT(val, 13, 3)
3340 #define VXGE_HAL_RX_QUEUE_START_Q7_SROW(val) vBIT(val, 18, 14)
3341 #define VXGE_HAL_RX_QUEUE_START_Q7_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3342 #define VXGE_HAL_RX_QUEUE_START_Q7_FDP_NONOFFLOAD_OUTST_FRMS(val)\
3343 vBIT(val, 55, 9)
3345 #define VXGE_HAL_RX_QUEUE_START_Q8_QUEUE_BANKS(val) vBIT(val, 6, 2)
3346 #define VXGE_HAL_RX_QUEUE_START_Q8_SBANK(val) vBIT(val, 13, 3)
3347 #define VXGE_HAL_RX_QUEUE_START_Q8_SROW(val) vBIT(val, 18, 14)
3348 #define VXGE_HAL_RX_QUEUE_START_Q8_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3350 #define VXGE_HAL_RX_QUEUE_START_Q9_QUEUE_BANKS(val) vBIT(val, 6, 2)
3351 #define VXGE_HAL_RX_QUEUE_START_Q9_SBANK(val) vBIT(val, 13, 3)
3352 #define VXGE_HAL_RX_QUEUE_START_Q9_SROW(val) vBIT(val, 18, 14)
3353 #define VXGE_HAL_RX_QUEUE_START_Q9_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3355 #define VXGE_HAL_RX_QUEUE_START_Q10_QUEUE_BANKS(val) vBIT(val, 6, 2)
3356 #define VXGE_HAL_RX_QUEUE_START_Q10_SBANK(val) vBIT(val, 13, 3)
3357 #define VXGE_HAL_RX_QUEUE_START_Q10_SROW(val) vBIT(val, 18, 14)
3358 #define VXGE_HAL_RX_QUEUE_START_Q10_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3360 #define VXGE_HAL_RX_QUEUE_START_Q11_QUEUE_BANKS(val) vBIT(val, 6, 2)
3361 #define VXGE_HAL_RX_QUEUE_START_Q11_SBANK(val) vBIT(val, 13, 3)
3362 #define VXGE_HAL_RX_QUEUE_START_Q11_SROW(val) vBIT(val, 18, 14)
3363 #define VXGE_HAL_RX_QUEUE_START_Q11_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3365 #define VXGE_HAL_RX_QUEUE_START_Q12_QUEUE_BANKS(val) vBIT(val, 6, 2)
3366 #define VXGE_HAL_RX_QUEUE_START_Q12_SBANK(val) vBIT(val, 13, 3)
3367 #define VXGE_HAL_RX_QUEUE_START_Q12_SROW(val) vBIT(val, 18, 14)
3368 #define VXGE_HAL_RX_QUEUE_START_Q12_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3370 #define VXGE_HAL_RX_QUEUE_START_Q13_QUEUE_BANKS(val) vBIT(val, 6, 2)
3371 #define VXGE_HAL_RX_QUEUE_START_Q13_SBANK(val) vBIT(val, 13, 3)
3372 #define VXGE_HAL_RX_QUEUE_START_Q13_SROW(val) vBIT(val, 18, 14)
3373 #define VXGE_HAL_RX_QUEUE_START_Q13_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3375 #define VXGE_HAL_RX_QUEUE_START_Q14_QUEUE_BANKS(val) vBIT(val, 6, 2)
3376 #define VXGE_HAL_RX_QUEUE_START_Q14_SBANK(val) vBIT(val, 13, 3)
3377 #define VXGE_HAL_RX_QUEUE_START_Q14_SROW(val) vBIT(val, 18, 14)
3378 #define VXGE_HAL_RX_QUEUE_START_Q14_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3380 #define VXGE_HAL_RX_QUEUE_START_Q15_QUEUE_BANKS(val) vBIT(val, 6, 2)
3381 #define VXGE_HAL_RX_QUEUE_START_Q15_SBANK(val) vBIT(val, 13, 3)
3382 #define VXGE_HAL_RX_QUEUE_START_Q15_SROW(val) vBIT(val, 18, 14)
3383 #define VXGE_HAL_RX_QUEUE_START_Q15_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3385 #define VXGE_HAL_RX_QUEUE_START_Q16_QUEUE_BANKS(val) vBIT(val, 6, 2)
3386 #define VXGE_HAL_RX_QUEUE_START_Q16_SBANK(val) vBIT(val, 13, 3)
3387 #define VXGE_HAL_RX_QUEUE_START_Q16_SROW(val) vBIT(val, 18, 14)
3388 #define VXGE_HAL_RX_QUEUE_START_Q16_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
3390 #define VXGE_HAL_RX_QUEUE_START_Q17_QUEUE_BANKS(val) vBIT(val, 6, 2)
3391 #define VXGE_HAL_RX_QUEUE_START_Q17_SBANK(val) vBIT(val, 13, 3)
3392 #define VXGE_HAL_RX_QUEUE_START_Q17_SROW(val) vBIT(val, 18, 14)
3394 #define VXGE_HAL_FM_DEFINITION_FM_SIZE(val) vBIT(val, 6, 2)
3395 #define VXGE_HAL_FM_DEFINITION_FM_COLUMNS(val) vBIT(val, 14, 2)
3396 #define VXGE_HAL_FM_DEFINITION_QUEUE_SPAV_MARGIN(val) vBIT(val, 16, 8)
3402 #define VXGE_HAL_TRAFFIC_CTRL_OFFLOAD_MAX_FRAMES(val) vBIT(val, 24, 8)
3403 #define VXGE_HAL_TRAFFIC_CTRL_NOFFLOAD_MAX_FRAMES(val) vBIT(val, 32, 8)
3404 #define VXGE_HAL_TRAFFIC_CTRL_MSP_MAX_FRAMES(val) vBIT(val, 40, 8)
3407 #define VXGE_HAL_XFMD_ARB_CTRL_EN_OFF(val) vBIT(val, 15, 17)
3408 #define VXGE_HAL_XFMD_ARB_CTRL_EN_NOFF(val) vBIT(val, 39, 17)
3410 #define VXGE_HAL_XFMD_ARB_CTRL1_PROMOTE_NOFF(val) vBIT(val, 6, 18)
3412 #define VXGE_HAL_RD_TRANC_CTRL_ARB(val) vBIT(val, 4, 4)
3414 #define VXGE_HAL_FM_ARB_CTRL(val) vBIT(val, 0, 8)
3415 #define VXGE_HAL_FM_ARB_TIMER(val) vBIT(val, 8, 8)
3416 #define VXGE_HAL_FM_ARB_EN_QHIST(val) vBIT(val, 16, 8)
3417 #define VXGE_HAL_FM_ARB_ACT_ARB_QHIST(val) vBIT(val, 28, 4)
3418 #define VXGE_HAL_FM_ARB_QHIST_CNT(val) vBIT(val, 32, 16)
3419 #define VXGE_HAL_FM_ARB_WR_DELAY_CNT(val) vBIT(val, 52, 4)
3420 #define VXGE_HAL_FM_ARB_WR_WINDOW_CNT(val) vBIT(val, 56, 8)
3422 #define VXGE_HAL_ARB_HP_CAL(val) vBIT(val, 0, 8)
3423 #define VXGE_HAL_ARB_XFMD_LAST_MASK(val) vBIT(val, 11, 5)
3424 #define VXGE_HAL_ARB_HP_XFMD_PRI(val) vBIT(val, 22, 2)
3426 #define VXGE_HAL_SETTINGS0_CTRL_FIFO_THR(val) vBIT(val, 4, 4)
3428 #define VXGE_HAL_FBMC_ECC_CFG_ENABLE(val) vBIT(val, 3, 5)
3500 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_SG_ERR(val) vBIT(val, 6, 2)
3501 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_SG_ERR(val) vBIT(val, 10, 6)
3503 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_DB_ERR(val) vBIT(val, 38, 2)
3504 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_DB_ERR(val) vBIT(val, 42, 6)
3510 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_SG_ERR(val) vBIT(val, 0, 8)
3511 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_SG_ERR(val) vBIT(val, 12, 4)
3512 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_SG_ERR(val) vBIT(val, 22, 2)
3513 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_SG_ERR(val) vBIT(val, 26, 6)
3514 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_DB_ERR(val) vBIT(val, 32, 8)
3515 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_DB_ERR(val) vBIT(val, 44, 4)
3516 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_DB_ERR(val) vBIT(val, 54, 2)
3517 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_DB_ERR(val) vBIT(val, 58, 6)
3544 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CACHE_PB_SG_ERR(val) vBIT(val, 0, 4)
3545 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CACHE_PB_SG_ERR(val) vBIT(val, 4, 4)
3546 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CACHE_PB_DB_ERR(val) vBIT(val, 8, 4)
3547 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CACHE_PB_DB_ERR(val) vBIT(val, 12, 4)
3589 #define VXGE_HAL_SSCC_CONFIG_HIT_SCHASH_INDEX_MSB(val) vBIT(val, 3, 5)
3590 #define VXGE_HAL_SSCC_CONFIG_HIT_SCHASH_INDEX_LSB(val) vBIT(val, 11, 5)
3591 #define VXGE_HAL_SSCC_CONFIG_TIMEOUT_VALUE(val) vBIT(val, 16, 16)
3593 #define VXGE_HAL_SSCC_CONFIG_ALRO_SCHASH_INDEX_MSB(val) vBIT(val, 43, 5)
3594 #define VXGE_HAL_SSCC_CONFIG_ALRO_SCHASH_INDEX_LSB(val) vBIT(val, 51, 5)
3597 #define VXGE_HAL_SSCC_MASK_0_IPV6_SA_TOP(val) vBIT(val, 0, 64)
3599 #define VXGE_HAL_SSCC_MASK_1_IPV6_SA_BOTTOM(val) vBIT(val, 0, 64)
3601 #define VXGE_HAL_SSCC_MASK_2_IPV6_DA_TOP(val) vBIT(val, 0, 64)
3603 #define VXGE_HAL_SSCC_MASK_3_IPV6_DA_BOTTOM(val) vBIT(val, 0, 64)
3605 #define VXGE_HAL_SSCC_MASK_4_IPV4_SA(val) vBIT(val, 0, 32)
3606 #define VXGE_HAL_SSCC_MASK_4_IPV4_DA(val) vBIT(val, 32, 32)
3608 #define VXGE_HAL_SSCC_MASK_5_TCP_SP(val) vBIT(val, 0, 16)
3609 #define VXGE_HAL_SSCC_MASK_5_TCP_DP(val) vBIT(val, 16, 16)
3610 #define VXGE_HAL_SSCC_MASK_5_VLANID(val) vBIT(val, 52, 12)
3639 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_PA_SG_ERR(val) vBIT(val, 0, 4)
3641 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_PA_DB_ERR(val) vBIT(val, 8, 4)
3678 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CACHE_PA_SG_ERR(val) vBIT(val, 0, 4)
3679 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_SG_ERR(val) vBIT(val, 4, 4)
3688 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CACHE_PA_DB_ERR(val) vBIT(val, 16, 4)
3689 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_DB_ERR(val) vBIT(val, 20, 4)
3733 #define VXGE_HAL_QCC_SRQ_CQRQ_POLL_TIMER(val) vBIT(val, 0, 32)
3734 #define VXGE_HAL_QCC_SRQ_CQRQ_MAX_EOL_POLLS(val) vBIT(val, 32, 8)
3737 #define VXGE_HAL_QCC_ERR_POLICY_CQM_CQE(val) vBIT(val, 4, 4)
3738 #define VXGE_HAL_QCC_ERR_POLICY_SQM_WQE(val) vBIT(val, 12, 4)
3739 #define VXGE_HAL_QCC_ERR_POLICY_SQM_SRQIR(val) vBIT(val, 22, 2)
3745 #define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_BAD_VPIN_CQRQ_ID(val) vBIT(val, 0, 16)
3746 #define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_BAD_CIN_CQRQ_ID(val) vBIT(val, 16, 16)
3747 #define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_MAX_CQE_GRP_CQRQ_ID(val) vBIT(val, 32, 16)
3748 #define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_CQM_CDR_CQRQ_ID(val) vBIT(val, 48, 16)
3750 #define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_BAD_VPIN_SRQ_ID(val) vBIT(val, 0, 16)
3751 #define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_BAD_SIN_SRQ_ID(val) vBIT(val, 16, 16)
3752 #define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_MAX_WQE_GRP_SRQ_ID(val) vBIT(val, 32, 16)
3753 #define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_SQM_WDR_SRQ_ID(val) vBIT(val, 48, 16)
3755 #define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_CCM_STATE_SERR(val) vBIT(val, 1, 7)
3756 #define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_FLM_HEAD_CQEGRP_ID(val) vBIT(val, 8, 24)
3757 #define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_FLM_TAIL_CQEGRP_ID(val)\
3758 vBIT(val, 40, 24)
3761 #define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_CCM_STATE_SERR(val) vBIT(val, 1, 7)
3762 #define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_FLM_HEAD_WQEGRP_ID(val) vBIT(val, 8, 24)
3763 #define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_FLM_TAIL_WQEGRP_ID(val)\
3764 vBIT(val, 40, 24)
3781 #define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PA_DB_ERR(val) vBIT(val, 0, 4)
3782 #define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PB_DB_ERR(val) vBIT(val, 4, 4)
3787 #define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PA_SG_ERR(val) vBIT(val, 16, 4)
3788 #define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PB_SG_ERR(val) vBIT(val, 20, 4)
3874 #define VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_SG_ERR(val) vBIT(val, 3, 2)
3875 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_IRAM_SG_ERR(val) vBIT(val, 5, 2)
3876 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_IRAM_SG_ERR(val) vBIT(val, 7, 2)
3877 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PA_SG_ERR(val) vBIT(val, 9, 2)
3878 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PB_SG_ERR(val) vBIT(val, 11, 2)
3884 #define VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_DB_ERR(val) vBIT(val, 35, 2)
3885 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_IRAM_DB_ERR(val) vBIT(val, 37, 2)
3886 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_IRAM_DB_ERR(val) vBIT(val, 39, 2)
3887 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PA_DB_ERR(val) vBIT(val, 41, 2)
3888 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PB_DB_ERR(val) vBIT(val, 43, 2)
3979 #define VXGE_HAL_TXPE_ERR_REG_TXPE_MSG2TXPE_SG_ERR(val) vBIT(val, 0, 2)
3982 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_SG_ERR(val) vBIT(val, 4, 2)
3983 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_IRAM_SG_ERR(val) vBIT(val, 6, 2)
3991 #define VXGE_HAL_TXPE_ERR_REG_TXPE_MSG2TXPE_DB_ERR(val) vBIT(val, 16, 2)
3994 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_DB_ERR(val) vBIT(val, 20, 2)
3995 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_IRAM_DB_ERR(val) vBIT(val, 22, 2)
4038 #define VXGE_HAL_TXPE_BCC_MEM_SG_ECC_ERR_REG_TXPE_BASE_TXPE_SG_ERR(val)\
4039 vBIT(val, 0, 32)
4040 #define VXGE_HAL_TXPE_BCC_MEM_SG_ECC_ERR_REG_TXPE_BASE_CDP_SG_ERR(val)\
4041 vBIT(val, 32, 32)
4045 #define VXGE_HAL_TXPE_BCC_MEM_DB_ECC_ERR_REG_TXPE_BASE_TXPE_DB_ERR(val)\
4046 vBIT(val, 0, 32)
4047 #define VXGE_HAL_TXPE_BCC_MEM_DB_ECC_ERR_REG_TXPE_BASE_CDP_DB_ERR(val)\
4048 vBIT(val, 32, 32)
4090 #define VXGE_HAL_SGRP_ALLOC_SGRP_ALLOC(val) vBIT(val, 0, 64)
4093 #define VXGE_HAL_SGRP_IWARP_LRO_ALLOC_LAST_IWARP_SGRP(val) vBIT(val, 11, 5)
4095 #define VXGE_HAL_RPE_CFG0_RCC_NBR_SLOTS(val) vBIT(val, 3, 5)
4096 #define VXGE_HAL_RPE_CFG0_RCC_NBR_FREE_SLOTS(val) vBIT(val, 11, 5)
4098 #define VXGE_HAL_RPE_CFG0_LL_SEND_MAX_SIZE(val) vBIT(val, 24, 8)
4116 #define VXGE_HAL_RPE_CFG1_DLM_RCMD_MAX_CREDITS(val) vBIT(val, 10, 6)
4117 #define VXGE_HAL_RPE_CFG1_MSG_RCMD_MAX_CREDITS(val) vBIT(val, 18, 6)
4118 #define VXGE_HAL_RPE_CFG1_PDM_RCMD_MAX_CREDITS(val) vBIT(val, 25, 7)
4119 #define VXGE_HAL_RPE_CFG1_RCQ_MAX_CREDITS(val) vBIT(val, 32, 8)
4120 #define VXGE_HAL_RPE_CFG1_RCQ_DLM_PRI(val) vBIT(val, 46, 2)
4121 #define VXGE_HAL_RPE_CFG1_RCQ_MSG_PRI(val) vBIT(val, 54, 2)
4122 #define VXGE_HAL_RPE_CFG1_RCQ_PDM_PRI(val) vBIT(val, 62, 2)
4124 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL0_PRI(val) vBIT(val, 6, 2)
4125 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL1_PRI(val) vBIT(val, 14, 2)
4126 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL2_PRI(val) vBIT(val, 22, 2)
4127 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL3_PRI(val) vBIT(val, 30, 2)
4128 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL4_PRI(val) vBIT(val, 38, 2)
4129 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL5_PRI(val) vBIT(val, 46, 2)
4157 #define VXGE_HAL_WQEOWN0_RPE_LRO_CTR(val) vBIT(val, 13, 19)
4158 #define VXGE_HAL_WQEOWN0_RPE_BS_CTR(val) vBIT(val, 45, 19)
4160 #define VXGE_HAL_WQEOWN1_RPE_IWARP_CTR(val) vBIT(val, 13, 19)
4162 #define VXGE_HAL_RPE_WQEOWN2_LRO_THRESHOLD(val) vBIT(val, 13, 19)
4163 #define VXGE_HAL_RPE_WQEOWN2_BS_THRESHOLD(val) vBIT(val, 45, 19)
4168 #define VXGE_HAL_PE_CTXT_S1_SIZE(val) vBIT(val, 10, 6)
4169 #define VXGE_HAL_PE_CTXT_S2_SIZE(val) vBIT(val, 26, 6)
4170 #define VXGE_HAL_PE_CTXT_S3_SIZE(val) vBIT(val, 42, 6)
4179 #define VXGE_HAL_PE_CFG_MAX_RXB2B(val) vBIT(val, 56, 8)
4183 #define VXGE_HAL_PE_STATS_CMD_ADDRESS(val) vBIT(val, 21, 11)
4185 #define VXGE_HAL_PE_STATS_DATA_PE_RETURNED(val) vBIT(val, 0, 64)
4187 #define VXGE_HAL_RXPE_FP_MASK_RXPE_FP_MASK(val) vBIT(val, 18, 46)
4192 #define VXGE_HAL_PE_XT_CTRL1_IRAM_ADDRESS(val) vBIT(val, 4, 12)
4210 #define VXGE_HAL_PE_XT_CTRL2_IRAM_WRITE_DATA(val) vBIT(val, 0, 64)
4214 #define VXGE_HAL_PE_XT_CTRL4_PE_IRAM_READ_DATA(val) vBIT(val, 0, 64)
4216 #define VXGE_HAL_PET_IWARP_COUNTERS_MASTER(val) vBIT(val, 0, 32)
4217 #define VXGE_HAL_PET_IWARP_COUNTERS_INTERVAL(val) vBIT(val, 40, 24)
4219 #define VXGE_HAL_PET_IWARP_SLOW_COUNTER_MASTER(val) vBIT(val, 0, 32)
4221 #define VXGE_HAL_PET_IWARP_TIMERS_TCP_NOW(val) vBIT(val, 0, 32)
4222 #define VXGE_HAL_PET_IWARP_TIMERS_TCP_SLOW_CLK(val) vBIT(val, 32, 32)
4224 #define VXGE_HAL_PET_LRO_CFG_START_VALUE(val) vBIT(val, 6, 2)
4226 #define VXGE_HAL_PET_LRO_COUNTERS_MASTER(val) vBIT(val, 0, 32)
4227 #define VXGE_HAL_PET_LRO_COUNTERS_INTERVAL(val) vBIT(val, 40, 24)
4234 #define VXGE_HAL_PE_VP_ACK_BLK_LIMIT(val) vBIT(val, 32, 32)
4236 #define VXGE_HAL_PE_VP_RIRR_BLK_LIMIT(val) vBIT(val, 0, 32)
4237 #define VXGE_HAL_PE_VP_LIRR_BLK_LIMIT(val) vBIT(val, 32, 32)
4240 #define VXGE_HAL_DLM_CFG_ACK_PTR_AE_LEVEL(val) vBIT(val, 12, 4)
4242 #define VXGE_HAL_DLM_CFG_LIRR_PTR_AE_LEVEL(val) vBIT(val, 28, 4)
4243 #define VXGE_HAL_DLM_CFG_RIRR_PTR_AE_LEVEL(val) vBIT(val, 44, 4)
4247 #define VXGE_HAL_TXPE_TOWI_CFG_TOWI_CACHE_SIZE(val) vBIT(val, 48, 8)
4248 #define VXGE_HAL_TXPE_TOWI_CFG_TOWI_DMA_THRESHOLD(val) vBIT(val, 56, 8)
4253 #define VXGE_HAL_TXPE_PMON_SAMPLE_PERIOD(val) vBIT(val, 16, 48)
4255 #define VXGE_HAL_TXPE_PMON_DOWNCOUNT_TXPE_REMAINDER(val) vBIT(val, 16, 48)
4257 #define VXGE_HAL_TXPE_PMON_EVENT_TXPE_STALL_CNT(val) vBIT(val, 16, 48)
4259 #define VXGE_HAL_TXPE_PMON_OTHER_TXPE_STALL_CNT(val) vBIT(val, 16, 48)
4263 #define VXGE_HAL_OES_INEVT_PRIORITY_0(val) vBIT(val, 5, 3)
4264 #define VXGE_HAL_OES_INEVT_PRIORITY_1(val) vBIT(val, 13, 3)
4265 #define VXGE_HAL_OES_INEVT_PRIORITY_2(val) vBIT(val, 21, 3)
4266 #define VXGE_HAL_OES_INEVT_PRIORITY_3(val) vBIT(val, 29, 3)
4267 #define VXGE_HAL_OES_INEVT_PRIORITY_4(val) vBIT(val, 37, 3)
4270 #define VXGE_HAL_OES_INBKBKEVT_PRIORITY_0(val) vBIT(val, 5, 3)
4271 #define VXGE_HAL_OES_INBKBKEVT_PRIORITY_1(val) vBIT(val, 13, 3)
4272 #define VXGE_HAL_OES_INBKBKEVT_PRIORITY_2(val) vBIT(val, 21, 3)
4273 #define VXGE_HAL_OES_INBKBKEVT_PRIORITY_3(val) vBIT(val, 29, 3)
4274 #define VXGE_HAL_OES_INBKBKEVT_PRIORITY_4(val) vBIT(val, 37, 3)
4276 #define VXGE_HAL_OES_INEVT_WRR0_SS_0(val) vBIT(val, 5, 3)
4277 #define VXGE_HAL_OES_INEVT_WRR0_SS_1(val) vBIT(val, 13, 3)
4278 #define VXGE_HAL_OES_INEVT_WRR0_SS_2(val) vBIT(val, 21, 3)
4279 #define VXGE_HAL_OES_INEVT_WRR0_SS_3(val) vBIT(val, 29, 3)
4280 #define VXGE_HAL_OES_INEVT_WRR0_SS_4(val) vBIT(val, 37, 3)
4281 #define VXGE_HAL_OES_INEVT_WRR0_SS_5(val) vBIT(val, 45, 3)
4282 #define VXGE_HAL_OES_INEVT_WRR0_SS_6(val) vBIT(val, 53, 3)
4283 #define VXGE_HAL_OES_INEVT_WRR0_SS_7(val) vBIT(val, 61, 3)
4285 #define VXGE_HAL_OES_INEVT_WRR1_SS_8(val) vBIT(val, 5, 3)
4286 #define VXGE_HAL_OES_INEVT_WRR1_SS_9(val) vBIT(val, 13, 3)
4287 #define VXGE_HAL_OES_INEVT_WRR1_SS_10(val) vBIT(val, 21, 3)
4288 #define VXGE_HAL_OES_INEVT_WRR1_SS_11(val) vBIT(val, 29, 3)
4289 #define VXGE_HAL_OES_INEVT_WRR1_SS_12(val) vBIT(val, 37, 3)
4290 #define VXGE_HAL_OES_INEVT_WRR1_SS_13(val) vBIT(val, 45, 3)
4291 #define VXGE_HAL_OES_INEVT_WRR1_SS_14(val) vBIT(val, 53, 3)
4293 #define VXGE_HAL_OES_PENDEVT_PRIORITY_0(val) vBIT(val, 5, 3)
4294 #define VXGE_HAL_OES_PENDEVT_PRIORITY_1(val) vBIT(val, 13, 3)
4295 #define VXGE_HAL_OES_PENDEVT_PRIORITY_2(val) vBIT(val, 21, 3)
4296 #define VXGE_HAL_OES_PENDEVT_PRIORITY_3(val) vBIT(val, 29, 3)
4297 #define VXGE_HAL_OES_PENDEVT_PRIORITY_4(val) vBIT(val, 37, 3)
4300 #define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_0(val) vBIT(val, 5, 3)
4301 #define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_1(val) vBIT(val, 13, 3)
4302 #define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_2(val) vBIT(val, 21, 3)
4303 #define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_3(val) vBIT(val, 29, 3)
4304 #define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_4(val) vBIT(val, 37, 3)
4306 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_0(val) vBIT(val, 5, 3)
4307 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_1(val) vBIT(val, 13, 3)
4308 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_2(val) vBIT(val, 21, 3)
4309 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_3(val) vBIT(val, 29, 3)
4310 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_4(val) vBIT(val, 37, 3)
4311 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_5(val) vBIT(val, 45, 3)
4312 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_6(val) vBIT(val, 53, 3)
4313 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_7(val) vBIT(val, 61, 3)
4315 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_8(val) vBIT(val, 5, 3)
4316 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_9(val) vBIT(val, 13, 3)
4317 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_10(val) vBIT(val, 21, 3)
4318 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_11(val) vBIT(val, 29, 3)
4319 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_12(val) vBIT(val, 37, 3)
4320 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_13(val) vBIT(val, 45, 3)
4321 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_14(val) vBIT(val, 53, 3)
4323 #define VXGE_HAL_OES_PEND_QUEUE_RX_PEND_THRESHOLD(val) vBIT(val, 27, 5)
4324 #define VXGE_HAL_OES_PEND_QUEUE_TX_PEND_THRESHOLD(val) vBIT(val, 57, 7)
4328 #define VXGE_HAL_ROCRC_BYPQ0_STAT_WATERMARK_RCQ_ROCRC_BYPQ0_STAT_WATERMARK(val)\
4329 vBIT(val, 11, 22)
4331 #define VXGE_HAL_ROCRC_BYPQ1_STAT_WATERMARK_RCQ_ROCRC_BYPQ1_STAT_WATERMARK(val)\
4332 vBIT(val, 11, 22)
4334 #define VXGE_HAL_ROCRC_BYPQ2_STAT_WATERMARK_RCQ_ROCRC_BYPQ2_STAT_WATERMARK(val)\
4335 vBIT(val, 11, 22)
4339 #define VXGE_HAL_RC_CFG2_BUFF1_SIZE(val) vBIT(val, 0, 16)
4340 #define VXGE_HAL_RC_CFG2_BUFF2_SIZE(val) vBIT(val, 16, 16)
4341 #define VXGE_HAL_RC_CFG2_BUFF3_SIZE(val) vBIT(val, 32, 16)
4342 #define VXGE_HAL_RC_CFG2_BUFF4_SIZE(val) vBIT(val, 48, 16)
4344 #define VXGE_HAL_RC_CFG3_BUFF5_SIZE(val) vBIT(val, 0, 16)
4347 #define VXGE_HAL_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val) vBIT(val, 11, 5)
4349 #define VXGE_HAL_RXDM_DBG_RD_ADDR(val) vBIT(val, 0, 12)
4352 #define VXGE_HAL_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vBIT(val, 0, 64)
4354 #define VXGE_HAL_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) vBIT(val, 59, 5)
4368 #define VXGE_HAL_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vBIT(val, 0, 32)
4370 #define VXGE_HAL_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vBIT(val, 3, 5)
4379 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val) vBIT(val, 0, 4)
4380 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val) vBIT(val, 4, 4)
4423 #define VXGE_HAL_CMC_L2_CLIENT_UQM_1_NUMBER(val) vBIT(val, 5, 3)
4425 #define VXGE_HAL_CMC_L2_CLIENT_SSC_L_NUMBER(val) vBIT(val, 5, 3)
4427 #define VXGE_HAL_CMC_L2_CLIENT_QCC_SQM_0_NUMBER(val) vBIT(val, 5, 3)
4429 #define VXGE_HAL_CMC_L2_CLIENT_DAM_0_NUMBER(val) vBIT(val, 5, 3)
4431 #define VXGE_HAL_CMC_L2_CLIENT_H2L_0_NUMBER(val) vBIT(val, 5, 3)
4433 #define VXGE_HAL_CMC_L2_CLIENT_STC_0_NUMBER(val) vBIT(val, 5, 3)
4435 #define VXGE_HAL_CMC_L2_CLIENT_XTMC_0_NUMBER(val) vBIT(val, 5, 3)
4437 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_0(val) vBIT(val, 5, 3)
4438 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_1(val) vBIT(val, 13, 3)
4439 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_2(val) vBIT(val, 21, 3)
4440 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_3(val) vBIT(val, 29, 3)
4441 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_4(val) vBIT(val, 37, 3)
4442 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_5(val) vBIT(val, 45, 3)
4443 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_6(val) vBIT(val, 53, 3)
4444 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_7(val) vBIT(val, 61, 3)
4446 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_8(val) vBIT(val, 5, 3)
4447 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_9(val) vBIT(val, 13, 3)
4448 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_10(val) vBIT(val, 21, 3)
4449 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_11(val) vBIT(val, 29, 3)
4450 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_12(val) vBIT(val, 37, 3)
4451 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_13(val) vBIT(val, 45, 3)
4452 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_14(val) vBIT(val, 53, 3)
4453 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_15(val) vBIT(val, 61, 3)
4455 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_16(val) vBIT(val, 5, 3)
4456 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_17(val) vBIT(val, 13, 3)
4457 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_18(val) vBIT(val, 21, 3)
4458 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_19(val) vBIT(val, 29, 3)
4459 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_20(val) vBIT(val, 37, 3)
4460 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_21(val) vBIT(val, 45, 3)
4461 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_22(val) vBIT(val, 53, 3)
4462 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_23(val) vBIT(val, 61, 3)
4464 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_24(val) vBIT(val, 5, 3)
4465 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_25(val) vBIT(val, 13, 3)
4466 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_26(val) vBIT(val, 21, 3)
4467 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_27(val) vBIT(val, 29, 3)
4469 #define VXGE_HAL_CMC_L3_CLIENT_QCC_SQM_1_NUMBER(val) vBIT(val, 5, 3)
4471 #define VXGE_HAL_CMC_L3_CLIENT_QCC_CQM_NUMBER(val) vBIT(val, 5, 3)
4473 #define VXGE_HAL_CMC_L3_CLIENT_DAM_1_NUMBER(val) vBIT(val, 5, 3)
4475 #define VXGE_HAL_CMC_L3_CLIENT_H2L_1_NUMBER(val) vBIT(val, 5, 3)
4477 #define VXGE_HAL_CMC_L3_CLIENT_STC_1_NUMBER(val) vBIT(val, 5, 3)
4479 #define VXGE_HAL_CMC_L3_CLIENT_XTMC_1_NUMBER(val) vBIT(val, 5, 3)
4481 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_0(val) vBIT(val, 5, 3)
4482 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_1(val) vBIT(val, 13, 3)
4483 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_2(val) vBIT(val, 21, 3)
4484 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_3(val) vBIT(val, 29, 3)
4485 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_4(val) vBIT(val, 37, 3)
4486 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_5(val) vBIT(val, 45, 3)
4487 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_6(val) vBIT(val, 53, 3)
4488 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_7(val) vBIT(val, 61, 3)
4490 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_8(val) vBIT(val, 5, 3)
4491 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_9(val) vBIT(val, 13, 3)
4492 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_10(val) vBIT(val, 21, 3)
4493 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_11(val) vBIT(val, 29, 3)
4494 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_12(val) vBIT(val, 37, 3)
4495 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_13(val) vBIT(val, 45, 3)
4496 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_14(val) vBIT(val, 53, 3)
4497 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_15(val) vBIT(val, 61, 3)
4499 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_16(val) vBIT(val, 5, 3)
4500 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_17(val) vBIT(val, 13, 3)
4501 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_18(val) vBIT(val, 21, 3)
4502 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_19(val) vBIT(val, 29, 3)
4503 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_20(val) vBIT(val, 37, 3)
4505 #define VXGE_HAL_CMC_USER_DOORBELL_PARTITION_BASE(val) vBIT(val, 8, 24)
4507 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_0_BASE(val) vBIT(val, 8, 24)
4509 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_1_BASE(val) vBIT(val, 8, 24)
4511 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_2_BASE(val) vBIT(val, 8, 24)
4513 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_3_BASE(val) vBIT(val, 8, 24)
4515 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_4_BASE(val) vBIT(val, 8, 24)
4517 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_5_BASE(val) vBIT(val, 8, 24)
4519 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_6_BASE(val) vBIT(val, 8, 24)
4521 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_7_BASE(val) vBIT(val, 8, 24)
4523 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_0_BASE(val) vBIT(val, 8, 24)
4525 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_1_BASE(val) vBIT(val, 8, 24)
4527 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_2_BASE(val) vBIT(val, 8, 24)
4529 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_3_BASE(val) vBIT(val, 8, 24)
4531 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_4_BASE(val) vBIT(val, 8, 24)
4533 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_5_BASE(val) vBIT(val, 8, 24)
4535 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_6_BASE(val) vBIT(val, 8, 24)
4537 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_7_BASE(val) vBIT(val, 8, 24)
4539 #define VXGE_HAL_CMC_WQE_OD_GROUP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4541 #define VXGE_HAL_CMC_ACK_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4543 #define VXGE_HAL_CMC_LIRR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4545 #define VXGE_HAL_CMC_RIRR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4547 #define VXGE_HAL_CMC_TCE_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4549 #define VXGE_HAL_CMC_HOQ_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4551 #define VXGE_HAL_CMC_STAG_VP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4553 #define VXGE_HAL_CMC_R_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4555 #define VXGE_HAL_CMC_CQRQ_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4557 #define VXGE_HAL_CMC_CQE_GROUP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4559 #define VXGE_HAL_CMC_P_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4561 #define VXGE_HAL_CMC_NCE_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4563 #define VXGE_HAL_CMC_BYPASS_QUEUE_PARTITION_BASE(val) vBIT(val, 8, 24)
4565 #define VXGE_HAL_CMC_H_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4567 #define VXGE_HAL_CMC_PBL_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4569 #define VXGE_HAL_CMC_LIT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4571 #define VXGE_HAL_CMC_SRQ_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
4573 #define VXGE_HAL_CMC_P_SCR_RECORD_SIZE(val) vBIT(val, 2, 6)
4575 #define VXGE_HAL_CMC_DEVICE_SELECT_CODE(val) vBIT(val, 5, 3)
4577 #define VXGE_HAL_G3IF_FIFO_DST_ECC_ENABLE(val) vBIT(val, 3, 5)
4583 #define VXGE_HAL_GXTMC_CFG_GPSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 20, 4)
4593 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val) vBIT(val, 0, 2)
4646 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vBIT(val, 54, 2)
4652 #define VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val) vBIT(val, 0, 8)
4653 #define VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val) vBIT(val, 8, 2)
4660 #define VXGE_HAL_CP_ERR_REG_CP_STC2CP_SG_ERR(val) vBIT(val, 16, 2)
4661 #define VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val) vBIT(val, 24, 8)
4662 #define VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val) vBIT(val, 32, 2)
4669 #define VXGE_HAL_CP_ERR_REG_CP_STC2CP_DB_ERR(val) vBIT(val, 40, 2)
4702 #define VXGE_HAL_CP_EXC_CAUSE_CP_CP_CAUSE(val) vBIT(val, 32, 32)
4706 #define VXGE_HAL_XTMC_IMG_CTRL0_LD_BANK_DEPTH(val) vBIT(val, 5, 3)
4710 #define VXGE_HAL_XTMC_IMG_CTRL0_ADDR(val) vBIT(val, 40, 24)
4712 #define VXGE_HAL_XTMC_IMG_CTRL1_DATA(val) vBIT(val, 0, 64)
4733 #define VXGE_HAL_PXTMC_CFG1_MAX_NBR_MXP_EVENTS(val) vBIT(val, 6, 2)
4734 #define VXGE_HAL_PXTMC_CFG1_MAX_NBR_UXP_EVENTS(val) vBIT(val, 14, 2)
4735 #define VXGE_HAL_PXTMC_CFG1_MAX_NBR_CXP_EVENTS(val) vBIT(val, 22, 2)
4739 #define VXGE_HAL_PXTMC_CFG1_PGSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 36, 4)
4741 #define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_SPARSE_BASE(val) vBIT(val, 5, 3)
4742 #define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_PACKED_BASE(val) vBIT(val, 13, 3)
4743 #define VXGE_HAL_XTMC_MEM_CFG_SHARED_SRAM_BASE(val) vBIT(val, 21, 3)
4744 #define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_SIZE(val) vBIT(val, 29, 3)
4745 #define VXGE_HAL_XTMC_MEM_CFG_SRAM_SPARSE_BASE_ADDR(val) vBIT(val, 32, 16)
4746 #define VXGE_HAL_XTMC_MEM_CFG_SRAM_PACKED_BASE_ADDR(val) vBIT(val, 48, 16)
4748 #define VXGE_HAL_XTMC_MEM_BYPASS_CFG_CTXT_MEM_SPARSE_BASE(val) vBIT(val, 5, 3)
4749 #define VXGE_HAL_XTMC_MEM_BYPASS_CFG_CTXT_MEM_PACKED_BASE(val) vBIT(val, 13, 3)
4750 #define VXGE_HAL_XTMC_MEM_BYPASS_CFG_SHARED_SRAM_BASE(val) vBIT(val, 21, 3)
4752 #define VXGE_HAL_XTMC_CXP_REGION0_START_ADDR(val) vBIT(val, 0, 32)
4753 #define VXGE_HAL_XTMC_CXP_REGION0_END_ADDR(val) vBIT(val, 32, 32)
4755 #define VXGE_HAL_XTMC_MXP_REGION0_START_ADDR(val) vBIT(val, 0, 32)
4756 #define VXGE_HAL_XTMC_MXP_REGION0_END_ADDR(val) vBIT(val, 32, 32)
4758 #define VXGE_HAL_XTMC_UXP_REGION0_START_ADDR(val) vBIT(val, 0, 32)
4759 #define VXGE_HAL_XTMC_UXP_REGION0_END_ADDR(val) vBIT(val, 32, 32)
4761 #define VXGE_HAL_XTMC_CXP_REGION1_START_ADDR(val) vBIT(val, 0, 32)
4762 #define VXGE_HAL_XTMC_CXP_REGION1_END_ADDR(val) vBIT(val, 32, 32)
4764 #define VXGE_HAL_XTMC_MXP_REGION1_START_ADDR(val) vBIT(val, 0, 32)
4765 #define VXGE_HAL_XTMC_MXP_REGION1_END_ADDR(val) vBIT(val, 32, 32)
4767 #define VXGE_HAL_XTMC_UXP_REGION1_START_ADDR(val) vBIT(val, 0, 32)
4768 #define VXGE_HAL_XTMC_UXP_REGION1_END_ADDR(val) vBIT(val, 32, 32)
4770 #define VXGE_HAL_XTMC_CXP_REGION2_START_ADDR(val) vBIT(val, 0, 32)
4771 #define VXGE_HAL_XTMC_CXP_REGION2_END_ADDR(val) vBIT(val, 32, 32)
4773 #define VXGE_HAL_XTMC_MXP_REGION2_START_ADDR(val) vBIT(val, 0, 32)
4774 #define VXGE_HAL_XTMC_MXP_REGION2_END_ADDR(val) vBIT(val, 32, 32)
4776 #define VXGE_HAL_XTMC_UXP_REGION2_START_ADDR(val) vBIT(val, 0, 32)
4777 #define VXGE_HAL_XTMC_UXP_REGION2_END_ADDR(val) vBIT(val, 32, 32)
4869 #define VXGE_HAL_MSG_DISPATCH_VPATH_CUTOFF(val) vBIT(val, 59, 5)
4882 #define VXGE_HAL_MSG_EXC_CAUSE_MP_MXP(val) vBIT(val, 0, 32)
4883 #define VXGE_HAL_MSG_EXC_CAUSE_UP_UXP(val) vBIT(val, 32, 32)
4889 #define VXGE_HAL_MSG_DIRECT_PIC_UMQ_VPA(val) vBIT(val, 59, 5)
4891 #define VXGE_HAL_UMQ_IR_TEST_VPA_NUMBER(val) vBIT(val, 0, 5)
4893 #define VXGE_HAL_UMQ_IR_TEST_BYTE_VALUE_START(val) vBIT(val, 0, 32)
4994 #define VXGE_HAL_UMQ_BWR_PFCH_INIT_NUMBER(val) vBIT(val, 0, 8)
4998 #define VXGE_HAL_UMQ_BWR_EOL_POLL_LATENCY(val) vBIT(val, 32, 32)
5013 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val)\
5014 vBIT(val, 2, 2)
5015 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val)\
5016 vBIT(val, 4, 2)
5019 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val)\
5020 vBIT(val, 8, 2)
5021 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val)\
5022 vBIT(val, 10, 2)
5025 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val)\
5026 vBIT(val, 14, 2)
5027 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val)\
5028 vBIT(val, 16, 2)
5029 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) vBIT(val, 18, 2)
5030 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val) vBIT(val, 20, 2)
5037 #define VXGE_HAL_FAU_GLOBAL_CFG_ARB_ALG(val) vBIT(val, 2, 2)
5039 #define VXGE_HAL_RX_DATAPATH_UTIL_FAU_RX_UTILIZATION(val) vBIT(val, 7, 9)
5040 #define VXGE_HAL_RX_DATAPATH_UTIL_RX_UTIL_CFG(val) vBIT(val, 16, 4)
5041 #define VXGE_HAL_RX_DATAPATH_UTIL_FAU_RX_FRAC_UTIL(val) vBIT(val, 20, 4)
5042 #define VXGE_HAL_RX_DATAPATH_UTIL_RX_PKT_WEIGHT(val) vBIT(val, 24, 4)
5050 #define VXGE_HAL_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) vBIT(val, 32, 32)
5053 #define VXGE_HAL_FAU_AUTO_LRO_CONTROL_FRAME_COUNT(val) vBIT(val, 8, 24)
5054 #define VXGE_HAL_FAU_AUTO_LRO_CONTROL_TIMER_VALUE(val) vBIT(val, 32, 32)
5056 #define VXGE_HAL_FAU_AUTO_LRO_DATA_0_SOURCE_VPATH(val) vBIT(val, 3, 5)
5059 #define VXGE_HAL_FAU_AUTO_LRO_DATA_0_VLAN_VID(val) vBIT(val, 20, 12)
5060 #define VXGE_HAL_FAU_AUTO_LRO_DATA_0_TCP_DEST_PORT(val) vBIT(val, 32, 16)
5061 #define VXGE_HAL_FAU_AUTO_LRO_DATA_0_TCP_SOURCE_PORT(val) vBIT(val, 48, 16)
5063 #define VXGE_HAL_FAU_AUTO_LRO_DATA_1_IP_SOURCE_ADDR_0(val) vBIT(val, 0, 64)
5065 #define VXGE_HAL_FAU_AUTO_LRO_DATA_2_IP_SOURCE_ADDR_1(val) vBIT(val, 0, 64)
5067 #define VXGE_HAL_FAU_AUTO_LRO_DATA_3_IP_DEST_ADDR_0(val) vBIT(val, 0, 64)
5069 #define VXGE_HAL_FAU_AUTO_LRO_DATA_4_IP_DEST_ADDR_1(val) vBIT(val, 0, 64)
5073 #define VXGE_HAL_FAU_LAG_CFG_COLL_ALG(val) vBIT(val, 2, 2)
5083 #define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_COL_INDX(val) vBIT(val, 0, 12)
5084 #define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_FLAG(val) vBIT(val, 26, 2)
5085 #define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_RXC(val) vBIT(val, 28, 4)
5086 #define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_RXD(val) vBIT(val, 32, 32)
5114 #define VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val) vBIT(val, 18, 2)
5115 #define VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val) vBIT(val, 22, 2)
5128 #define VXGE_HAL_TX_DATAPATH_UTIL_TPA_TX_UTILIZATION(val) vBIT(val, 7, 9)
5129 #define VXGE_HAL_TX_DATAPATH_UTIL_TX_UTIL_CFG(val) vBIT(val, 16, 4)
5130 #define VXGE_HAL_TX_DATAPATH_UTIL_TPA_TX_FRAC_UTIL(val) vBIT(val, 20, 4)
5131 #define VXGE_HAL_TX_DATAPATH_UTIL_TX_PKT_WEIGHT(val) vBIT(val, 24, 4)
5133 #define VXGE_HAL_ORP_CFG_FIFO_CREDITS(val) vBIT(val, 5, 3)
5142 #define VXGE_HAL_ORP_LRO_EVENTS_ORP_LRO_EVENTS(val) vBIT(val, 0, 64)
5144 #define VXGE_HAL_ORP_BS_EVENTS_ORP_BS_EVENTS(val) vBIT(val, 0, 64)
5146 #define VXGE_HAL_ORP_IWARP_EVENTS_ORP_IWARP_EVENTS(val) vBIT(val, 0, 64)
5148 #define VXGE_HAL_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) vBIT(val, 32, 32)
5182 #define VXGE_HAL_TXMAC_GEN_CFG1_IFS_STRETCH_RATIO(val) vBIT(val, 40, 16)
5183 #define VXGE_HAL_TXMAC_GEN_CFG1_IFS_NUM_EXTENSION(val) vBIT(val, 59, 5)
5187 #define VXGE_HAL_TXMAC_ERR_INJECT_CFG_INJECTOR_ERROR_RATE(val) vBIT(val, 0, 32)
5190 #define VXGE_HAL_TXMAC_FRMGEN_CFG_MODE(val) vBIT(val, 6, 2)
5191 #define VXGE_HAL_TXMAC_FRMGEN_CFG_PERIOD(val) vBIT(val, 8, 4)
5193 #define VXGE_HAL_TXMAC_FRMGEN_CFG_VPATH_VECTOR(val) vBIT(val, 19, 17)
5194 #define VXGE_HAL_TXMAC_FRMGEN_CFG_SRC_VPATH(val) vBIT(val, 39, 5)
5195 #define VXGE_HAL_TXMAC_FRMGEN_CFG_HOST_STEERING(val) vBIT(val, 44, 2)
5196 #define VXGE_HAL_TXMAC_FRMGEN_CFG_IFS_SEL(val) vBIT(val, 47, 3)
5198 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_PATTERN_SEL(val) vBIT(val, 2, 2)
5199 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_DA_SEL(val) vBIT(val, 6, 2)
5201 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_MIN_LEN(val) vBIT(val, 14, 14)
5202 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_MAX_LEN(val) vBIT(val, 30, 14)
5203 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_LT_FIELD(val) vBIT(val, 44, 16)
5204 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_DATA_SEL(val) vBIT(val, 62, 2)
5206 #define VXGE_HAL_TXMAC_FRMGEN_DATA_FRMDATA(val) vBIT(val, 0, 64)
5208 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val) vBIT(val, 0, 8)
5209 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val) vBIT(val, 8, 8)
5210 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val) vBIT(val, 16, 8)
5214 #define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) vBIT(val, 1, 7)
5215 #define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val) vBIT(val, 8, 4)
5216 #define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) vBIT(val, 12, 4)
5217 #define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val) vBIT(val, 16, 4)
5222 #define VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(val) vBIT(val, 8, 8)
5224 #define VXGE_HAL_TXMAC_CFG1_PORT_AVG_IPG(val) vBIT(val, 40, 8)
5234 #define VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT(val) vBIT(val, 16, 16)
5235 #define VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val)\
5236 vBIT(val, 32, 16)
5240 #define VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(val) vBIT(val, 6, 2)
5242 #define VXGE_HAL_LAG_TX_CFG_COLL_MAX_DELAY(val) vBIT(val, 16, 16)
5244 #define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) vBIT(val, 0, 8)
5245 #define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val)\
5246 vBIT(val, 8, 8)
5247 #define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val)\
5248 vBIT(val, 16, 8)
5252 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_LANE_CHAR1(val) vBIT(val, 1, 3)
5254 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXD_CHAR1(val) vBIT(val, 8, 8)
5255 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_LANE_CHAR2(val) vBIT(val, 17, 3)
5257 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXD_CHAR2(val) vBIT(val, 24, 8)
5259 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_BEHAV_CHAR2_NUM_CHAR(val)\
5260 vBIT(val, 40, 16)
5263 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE0(val) vBIT(val, 8, 8)
5265 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE1(val) vBIT(val, 24, 8)
5267 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE2(val) vBIT(val, 40, 8)
5269 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE3(val) vBIT(val, 56, 8)
5272 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE0(val) vBIT(val, 8, 8)
5274 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE1(val) vBIT(val, 24, 8)
5276 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE2(val) vBIT(val, 40, 8)
5278 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE3(val) vBIT(val, 56, 8)
5281 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_BEHAV_COLUMN2_NUM_COL(val)\
5282 vBIT(val, 8, 16)
5286 #define VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_ACTIVE_VPLANE(val)\
5287 vBIT(val, 0, 17)
5288 #define VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_VPLANE_COUNT(val)\
5289 vBIT(val, 20, 8)
5292 #define VXGE_HAL_SHAREDIO_STATUS_PCI_RX_ILLEGAL_TLP_VPLANE_VAL(val)\
5293 vBIT(val, 36, 8)
5295 #define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_PD(val) vBIT(val, 4, 12)
5296 #define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_NPD(val) vBIT(val, 20, 12)
5297 #define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_CPLD(val) vBIT(val, 36, 12)
5302 #define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_PH(val) vBIT(val, 0, 8)
5303 #define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_NPH(val) vBIT(val, 8, 8)
5304 #define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_CPLH(val) vBIT(val, 16, 8)
5309 #define VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_PD(val) vBIT(val, 4, 12)
5310 #define VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_NPD(val)\
5311 vBIT(val, 20, 12)
5312 #define VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_CPLD(val)\
5313 vBIT(val, 36, 12)
5315 #define VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_PH(val) vBIT(val, 0, 8)
5316 #define VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_NPH(val) vBIT(val, 8, 8)
5317 #define VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_CPLH(val)\
5318 vBIT(val, 16, 8)
5320 #define VXGE_HAL_CRDT_STATUS5_PCI_DEPL_PH(val) vBIT(val, 0, 17)
5321 #define VXGE_HAL_CRDT_STATUS5_PCI_DEPL_NPH(val) vBIT(val, 20, 17)
5322 #define VXGE_HAL_CRDT_STATUS5_PCI_DEPL_CPLH(val) vBIT(val, 40, 17)
5324 #define VXGE_HAL_CRDT_STATUS6_PCI_DEPL_PD(val) vBIT(val, 0, 17)
5325 #define VXGE_HAL_CRDT_STATUS6_PCI_DEPL_NPD(val) vBIT(val, 20, 17)
5326 #define VXGE_HAL_CRDT_STATUS6_PCI_DEPL_CPLD(val) vBIT(val, 40, 17)
5328 #define VXGE_HAL_CRDT_STATUS7_PCI_ABS_PD(val) vBIT(val, 4, 12)
5329 #define VXGE_HAL_CRDT_STATUS7_PCI_ABS_NPD(val) vBIT(val, 20, 12)
5330 #define VXGE_HAL_CRDT_STATUS7_PCI_ABS_CPLD(val) vBIT(val, 36, 12)
5335 #define VXGE_HAL_CRDT_STATUS8_PCI_ABS_PH(val) vBIT(val, 0, 8)
5336 #define VXGE_HAL_CRDT_STATUS8_PCI_ABS_NPH(val) vBIT(val, 8, 8)
5337 #define VXGE_HAL_CRDT_STATUS8_PCI_ABS_CPLH(val) vBIT(val, 16, 8)
5342 #define VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_RMSG(val) vBIT(val, 0, 64)
5346 #define VXGE_HAL_PCIE_LANE_CFG1_RX_0_SEL(val) vBIT(val, 1, 3)
5347 #define VXGE_HAL_PCIE_LANE_CFG1_RX_1_SEL(val) vBIT(val, 5, 3)
5348 #define VXGE_HAL_PCIE_LANE_CFG1_RX_2_SEL(val) vBIT(val, 9, 3)
5349 #define VXGE_HAL_PCIE_LANE_CFG1_RX_3_SEL(val) vBIT(val, 13, 3)
5350 #define VXGE_HAL_PCIE_LANE_CFG1_RX_4_SEL(val) vBIT(val, 17, 3)
5351 #define VXGE_HAL_PCIE_LANE_CFG1_RX_5_SEL(val) vBIT(val, 21, 3)
5352 #define VXGE_HAL_PCIE_LANE_CFG1_RX_6_SEL(val) vBIT(val, 25, 3)
5353 #define VXGE_HAL_PCIE_LANE_CFG1_RX_7_SEL(val) vBIT(val, 29, 3)
5354 #define VXGE_HAL_PCIE_LANE_CFG1_TX_0_SEL(val) vBIT(val, 33, 3)
5355 #define VXGE_HAL_PCIE_LANE_CFG1_TX_1_SEL(val) vBIT(val, 37, 3)
5356 #define VXGE_HAL_PCIE_LANE_CFG1_TX_2_SEL(val) vBIT(val, 41, 3)
5357 #define VXGE_HAL_PCIE_LANE_CFG1_TX_3_SEL(val) vBIT(val, 45, 3)
5358 #define VXGE_HAL_PCIE_LANE_CFG1_TX_4_SEL(val) vBIT(val, 49, 3)
5359 #define VXGE_HAL_PCIE_LANE_CFG1_TX_5_SEL(val) vBIT(val, 53, 3)
5360 #define VXGE_HAL_PCIE_LANE_CFG1_TX_6_SEL(val) vBIT(val, 57, 3)
5361 #define VXGE_HAL_PCIE_LANE_CFG1_TX_7_SEL(val) vBIT(val, 61, 3)
5365 #define VXGE_HAL_PCICFG_NO_TO_FUNC_CFG_PCICFG_NO_TO_FUNC_CFG(val)\
5366 vBIT(val, 3, 5)
5368 #define VXGE_HAL_RESOURCE_TO_VPLANE_CFG_RESOURCE_TO_VPLANE_CFG(val)\
5369 vBIT(val, 3, 5)
5371 #define VXGE_HAL_PCICFG_NO_TO_VPLANE_CFG_PCICFG_NO_TO_VPLANE_CFG(val)\
5372 vBIT(val, 3, 5)
5378 #define VXGE_HAL_GENERAL_CFG_RST_CPLTO_VAL(val) vBIT(val, 4, 4)
5380 #define VXGE_HAL_GENERAL_CFG_INIT_OSD_COUNT(val) vBIT(val, 12, 8)
5381 #define VXGE_HAL_GENERAL_CFG_INIT_SHC(val) vBIT(val, 20, 8)
5382 #define VXGE_HAL_GENERAL_CFG_INITOSD_VERSION(val) vBIT(val, 29, 3)
5384 #define VXGE_HAL_GENERAL_CFG_FC_UPDT_FREQ_VAL(val) vBIT(val, 36, 4)
5404 #define VXGE_HAL_BIST_CFG_JTAG_BIST_COMPLETION_CODE(val) vBIT(val, 8, 4)
5409 #define VXGE_HAL_SHOW_SRIOV_CAP_SHOW_SRIOV_CAP(val) vBIT(val, 0, 9)
5411 #define VXGE_HAL_LINK_RST_WAIT_CNT_LINK_RST_WAIT_CNT(val) vBIT(val, 0, 16)
5413 #define VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_PD(val) vBIT(val, 4, 12)
5414 #define VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_NPD(val) vBIT(val, 20, 12)
5415 #define VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_CPLD(val) vBIT(val, 36, 12)
5417 #define VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_PH(val) vBIT(val, 0, 8)
5418 #define VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_NPH(val) vBIT(val, 8, 8)
5419 #define VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_CPLH(val) vBIT(val, 16, 8)
5421 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_PD(val)\
5422 vBIT(val, 4, 12)
5423 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_NPD(val)\
5424 vBIT(val, 20, 12)
5425 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_CPLD(val)\
5426 vBIT(val, 36, 12)
5431 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_PH(val)\
5432 vBIT(val, 0, 8)
5433 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_NPH(val)\
5434 vBIT(val, 8, 8)
5435 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_CPLH(val)\
5436 vBIT(val, 16, 8)
5441 #define VXGE_HAL_ARBITER_CFG_CPL_PRIORITY(val) vBIT(val, 2, 2)
5442 #define VXGE_HAL_ARBITER_CFG_MRD_PRIORITY(val) vBIT(val, 6, 2)
5443 #define VXGE_HAL_ARBITER_CFG_MWR_PRIORITY(val) vBIT(val, 10, 2)
5445 #define VXGE_HAL_ARBITER_CFG_CALSTATE0_PRIORITY(val) vBIT(val, 18, 2)
5446 #define VXGE_HAL_ARBITER_CFG_CALSTATE1_PRIORITY(val) vBIT(val, 22, 2)
5447 #define VXGE_HAL_ARBITER_CFG_CALSTATE2_PRIORITY(val) vBIT(val, 26, 2)
5448 #define VXGE_HAL_ARBITER_CFG_CALSTATE3_PRIORITY(val) vBIT(val, 30, 2)
5449 #define VXGE_HAL_ARBITER_CFG_CALSTATE4_PRIORITY(val) vBIT(val, 34, 2)
5450 #define VXGE_HAL_ARBITER_CFG_CALSTATE5_PRIORITY(val) vBIT(val, 38, 2)
5452 #define VXGE_HAL_SERDES_CFG1_TX_CLOCK_ALIGN(val) vBIT(val, 0, 8)
5453 #define VXGE_HAL_SERDES_CFG1_TX_CALC(val) vBIT(val, 8, 8)
5454 #define VXGE_HAL_SERDES_CFG1_TX_LVL(val) vBIT(val, 19, 5)
5455 #define VXGE_HAL_SERDES_CFG1_LOS_LVL(val) vBIT(val, 27, 5)
5457 #define VXGE_HAL_SERDES_CFG2_TX_0_BOOST(val) vBIT(val, 0, 4)
5458 #define VXGE_HAL_SERDES_CFG2_TX_1_BOOST(val) vBIT(val, 4, 4)
5459 #define VXGE_HAL_SERDES_CFG2_TX_2_BOOST(val) vBIT(val, 8, 4)
5460 #define VXGE_HAL_SERDES_CFG2_TX_3_BOOST(val) vBIT(val, 12, 4)
5461 #define VXGE_HAL_SERDES_CFG2_TX_4_BOOST(val) vBIT(val, 16, 4)
5462 #define VXGE_HAL_SERDES_CFG2_TX_5_BOOST(val) vBIT(val, 20, 4)
5463 #define VXGE_HAL_SERDES_CFG2_TX_6_BOOST(val) vBIT(val, 24, 4)
5464 #define VXGE_HAL_SERDES_CFG2_TX_7_BOOST(val) vBIT(val, 28, 4)
5465 #define VXGE_HAL_SERDES_CFG2_TX_0_ATTEN(val) vBIT(val, 33, 3)
5466 #define VXGE_HAL_SERDES_CFG2_TX_1_ATTEN(val) vBIT(val, 37, 3)
5467 #define VXGE_HAL_SERDES_CFG2_TX_2_ATTEN(val) vBIT(val, 41, 3)
5468 #define VXGE_HAL_SERDES_CFG2_TX_3_ATTEN(val) vBIT(val, 45, 3)
5469 #define VXGE_HAL_SERDES_CFG2_TX_4_ATTEN(val) vBIT(val, 49, 3)
5470 #define VXGE_HAL_SERDES_CFG2_TX_5_ATTEN(val) vBIT(val, 53, 3)
5471 #define VXGE_HAL_SERDES_CFG2_TX_6_ATTEN(val) vBIT(val, 57, 3)
5472 #define VXGE_HAL_SERDES_CFG2_TX_7_ATTEN(val) vBIT(val, 61, 3)
5474 #define VXGE_HAL_SERDES_CFG3_TX_0_EDGERATE(val) vBIT(val, 2, 2)
5475 #define VXGE_HAL_SERDES_CFG3_TX_1_EDGERATE(val) vBIT(val, 6, 2)
5476 #define VXGE_HAL_SERDES_CFG3_TX_2_EDGERATE(val) vBIT(val, 10, 2)
5477 #define VXGE_HAL_SERDES_CFG3_TX_3_EDGERATE(val) vBIT(val, 14, 2)
5478 #define VXGE_HAL_SERDES_CFG3_TX_4_EDGERATE(val) vBIT(val, 18, 2)
5479 #define VXGE_HAL_SERDES_CFG3_TX_5_EDGERATE(val) vBIT(val, 22, 2)
5480 #define VXGE_HAL_SERDES_CFG3_TX_6_EDGERATE(val) vBIT(val, 26, 2)
5481 #define VXGE_HAL_SERDES_CFG3_TX_7_EDGERATE(val) vBIT(val, 30, 2)
5482 #define VXGE_HAL_SERDES_CFG3_RX_0_EQ_VAL(val) vBIT(val, 33, 3)
5483 #define VXGE_HAL_SERDES_CFG3_RX_1_EQ_VAL(val) vBIT(val, 37, 3)
5484 #define VXGE_HAL_SERDES_CFG3_RX_2_EQ_VAL(val) vBIT(val, 41, 3)
5485 #define VXGE_HAL_SERDES_CFG3_RX_3_EQ_VAL(val) vBIT(val, 45, 3)
5486 #define VXGE_HAL_SERDES_CFG3_RX_4_EQ_VAL(val) vBIT(val, 49, 3)
5487 #define VXGE_HAL_SERDES_CFG3_RX_5_EQ_VAL(val) vBIT(val, 53, 3)
5488 #define VXGE_HAL_SERDES_CFG3_RX_6_EQ_VAL(val) vBIT(val, 57, 3)
5489 #define VXGE_HAL_SERDES_CFG3_RX_7_EQ_VAL(val) vBIT(val, 61, 3)
5491 #define VXGE_HAL_VHLABEL_TO_VPLANE_CFG_VHLABEL_TO_VPLANE_CFG(val)\
5492 vBIT(val, 3, 5)
5494 #define VXGE_HAL_MRPCIM_TO_SRPCIM_VPLANE_WMSG_WMSG(val) vBIT(val, 0, 64)
5498 #define VXGE_HAL_DEBUG_STATS0_RSTDROP_MSG(val) vBIT(val, 0, 32)
5499 #define VXGE_HAL_DEBUG_STATS0_RSTDROP_CPL(val) vBIT(val, 32, 32)
5501 #define VXGE_HAL_DEBUG_STATS1_RSTDROP_CLIENT0(val) vBIT(val, 0, 32)
5502 #define VXGE_HAL_DEBUG_STATS1_RSTDROP_CLIENT1(val) vBIT(val, 32, 32)
5504 #define VXGE_HAL_DEBUG_STATS2_RSTDROP_CLIENT2(val) vBIT(val, 0, 32)
5506 #define VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_PH(val) vBIT(val, 0, 16)
5507 #define VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_NPH(val) vBIT(val, 16, 16)
5508 #define VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_CPLH(val) vBIT(val, 32, 16)
5510 #define VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_PD(val) vBIT(val, 0, 16)
5511 #define VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_NPD(val) vBIT(val, 16, 16)
5512 #define VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_CPLD(val) vBIT(val, 32, 16)
5516 #define VXGE_HAL_RC_RXDMEM_END_OFST_RC_RXDMEM_END_OFST(val) vBIT(val, 49, 8)
5755 #define VXGE_HAL_SRPCIM_TO_MRPCIM_ALARM_REG_ALARM(val) vBIT(val, 0, 17)
5759 #define VXGE_HAL_VPATH_TO_MRPCIM_ALARM_REG_ALARM(val) vBIT(val, 0, 17)
5782 #define VXGE_HAL_SPLIT_TABLE_STATUS1_SCPL_TAG_ENTRY1(val) vBIT(val, 0, 64)
5784 #define VXGE_HAL_SPLIT_TABLE_STATUS2_SCPL_TAG_ENTRY2(val) vBIT(val, 0, 64)
5786 #define VXGE_HAL_SPLIT_TABLE_STATUS3_SCPL_TAG_ENTRY3(val) vBIT(val, 0, 64)
5788 #define VXGE_HAL_MRPCIM_GENERAL_STATUS1_INI_RCPL_ERRSYND(val) vBIT(val, 0, 8)
5790 #define VXGE_HAL_MRPCIM_GENERAL_STATUS1_SCPL_NUM_OUTSTANDING_RDS(val)\
5791 vBIT(val, 18, 6)
5792 #define VXGE_HAL_MRPCIM_GENERAL_STATUS1_TGT_VENDOR_MSG_PAYLOAD(val)\
5793 vBIT(val, 32, 32)
5795 #define VXGE_HAL_MRPCIM_GENERAL_STATUS2_CFGM_TIMEOUT_ADDR(val) vBIT(val, 6, 10)
5796 #define VXGE_HAL_MRPCIM_GENERAL_STATUS2_RIC_TIMEOUT_ADDR(val) vBIT(val, 22, 10)
5797 #define VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_CLIENT(val)\
5798 vBIT(val, 34, 2)
5800 #define VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_ADDR(val) vBIT(val, 44, 20)
5802 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_PIFM_TIMEOUT_ADDR(val) vBIT(val, 0, 20)
5803 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_NOT_MEM_TLP_FMT(val)\
5804 vBIT(val, 21, 2)
5805 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_NOT_MEM_TLP_TYPE(val)\
5806 vBIT(val, 23, 5)
5807 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_UNKNOWN_MEM_TLP_FMT(val)\
5808 vBIT(val, 29, 2)
5809 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_UNKNOWN_MEM_TLP_TYPE(val)\
5810 vBIT(val, 31, 5)
5863 #define VXGE_HAL_KDFCCTL_DBG_STATUS_KDFCCTL_ADDR_ERR(val) vBIT(val, 2, 22)
5864 #define VXGE_HAL_KDFCCTL_DBG_STATUS_KDFCCTL_FIFO_NO_ERR(val) vBIT(val, 26, 6)
5866 #define VXGE_HAL_MSIX_ADDR_MSIX_ADDR(val) vBIT(val, 0, 64)
5868 #define VXGE_HAL_MSIX_TABLE_DATA(val) vBIT(val, 0, 32)
5871 #define VXGE_HAL_MSIX_CTL_VECTOR_NO(val) vBIT(val, 1, 7)
5894 #define VXGE_HAL_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val) vBIT(val, 13, 51)
5896 #define VXGE_HAL_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H(val)\
5897 vBIT(val, 0, 8)
5899 #define VXGE_HAL_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D(val)\
5900 vBIT(val, 4, 12)
5915 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(val)\
5916 vBIT(val, 47, 5)
5927 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS(val) vBIT(val, 20, 16)
5928 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE(val) vBIT(val, 36, 16)
5930 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG(val) vBIT(val, 56, 2)
5934 #define VXGE_HAL_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\
5935 vBIT(val, 0, 57)
5937 #define VXGE_HAL_ASIC_MODE_PIC(val) vBIT(val, 2, 2)
5941 #define VXGE_HAL_INI_TIMEOUT_VAL_MWR(val) vBIT(val, 0, 32)
5942 #define VXGE_HAL_INI_TIMEOUT_VAL_MRD(val) vBIT(val, 32, 32)
5950 #define VXGE_HAL_READ_ARBITER_WRDMA_PRIORITY(val) vBIT(val, 2, 2)
5951 #define VXGE_HAL_READ_ARBITER_RTDMA_PRIORITY(val) vBIT(val, 6, 2)
5952 #define VXGE_HAL_READ_ARBITER_DBLGEN_PRIORITY(val) vBIT(val, 10, 2)
5953 #define VXGE_HAL_READ_ARBITER_CALSTATE0_PRIORITY(val) vBIT(val, 14, 2)
5954 #define VXGE_HAL_READ_ARBITER_CALSTATE1_PRIORITY(val) vBIT(val, 18, 2)
5955 #define VXGE_HAL_READ_ARBITER_CALSTATE2_PRIORITY(val) vBIT(val, 22, 2)
5956 #define VXGE_HAL_READ_ARBITER_CALSTATE3_PRIORITY(val) vBIT(val, 26, 2)
5957 #define VXGE_HAL_READ_ARBITER_CALSTATE4_PRIORITY(val) vBIT(val, 30, 2)
5958 #define VXGE_HAL_READ_ARBITER_CALSTATE5_PRIORITY(val) vBIT(val, 34, 2)
5961 #define VXGE_HAL_WRITE_ARBITER_WRDMA_PRIORITY(val) vBIT(val, 2, 2)
5962 #define VXGE_HAL_WRITE_ARBITER_RTDMA_PRIORITY(val) vBIT(val, 6, 2)
5963 #define VXGE_HAL_WRITE_ARBITER_STATS_PRIORITY(val) vBIT(val, 10, 2)
5964 #define VXGE_HAL_WRITE_ARBITER_MSG_PRIORITY(val) vBIT(val, 14, 2)
5965 #define VXGE_HAL_WRITE_ARBITER_CALSTATE0_PRIORITY(val) vBIT(val, 18, 2)
5966 #define VXGE_HAL_WRITE_ARBITER_CALSTATE1_PRIORITY(val) vBIT(val, 22, 2)
5967 #define VXGE_HAL_WRITE_ARBITER_CALSTATE2_PRIORITY(val) vBIT(val, 26, 2)
5968 #define VXGE_HAL_WRITE_ARBITER_CALSTATE3_PRIORITY(val) vBIT(val, 30, 2)
5969 #define VXGE_HAL_WRITE_ARBITER_CALSTATE4_PRIORITY(val) vBIT(val, 34, 2)
5970 #define VXGE_HAL_WRITE_ARBITER_CALSTATE5_PRIORITY(val) vBIT(val, 38, 2)
5971 #define VXGE_HAL_WRITE_ARBITER_CALSTATE6_PRIORITY(val) vBIT(val, 42, 2)
5972 #define VXGE_HAL_WRITE_ARBITER_CALSTATE7_PRIORITY(val) vBIT(val, 46, 2)
5973 #define VXGE_HAL_WRITE_ARBITER_CALSTATE8_PRIORITY(val) vBIT(val, 50, 2)
5974 #define VXGE_HAL_WRITE_ARBITER_CALSTATE9_PRIORITY(val) vBIT(val, 52, 2)
5981 #define VXGE_HAL_PROGRAM_CFG0_I2C_SLAVE_ADDR(val) vBIT(val, 1, 7)
5985 #define VXGE_HAL_PROGRAM_CFG1_CFGM_TIMEOUT_LOAD_VAL(val) vBIT(val, 0, 32)
5986 #define VXGE_HAL_PROGRAM_CFG1_PIFM_TIMEOUT_LOAD_VAL(val) vBIT(val, 32, 32)
5988 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_0_NUM(val) vBIT(val, 3, 5)
5989 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_1_NUM(val) vBIT(val, 11, 5)
5990 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_2_NUM(val) vBIT(val, 19, 5)
5991 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_3_NUM(val) vBIT(val, 27, 5)
5992 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_4_NUM(val) vBIT(val, 35, 5)
5993 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_5_NUM(val) vBIT(val, 43, 5)
5994 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_6_NUM(val) vBIT(val, 51, 5)
5995 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_7_NUM(val) vBIT(val, 59, 5)
5997 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_8_NUM(val) vBIT(val, 3, 5)
5998 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_9_NUM(val) vBIT(val, 11, 5)
5999 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_10_NUM(val) vBIT(val, 19, 5)
6000 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_11_NUM(val) vBIT(val, 27, 5)
6001 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_12_NUM(val) vBIT(val, 35, 5)
6002 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_13_NUM(val) vBIT(val, 43, 5)
6003 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_14_NUM(val) vBIT(val, 51, 5)
6004 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_15_NUM(val) vBIT(val, 59, 5)
6006 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_16_NUM(val) vBIT(val, 3, 5)
6007 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_17_NUM(val) vBIT(val, 11, 5)
6008 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_18_NUM(val) vBIT(val, 19, 5)
6009 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_19_NUM(val) vBIT(val, 27, 5)
6010 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_20_NUM(val) vBIT(val, 35, 5)
6011 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_21_NUM(val) vBIT(val, 43, 5)
6012 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_22_NUM(val) vBIT(val, 51, 5)
6013 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_23_NUM(val) vBIT(val, 59, 5)
6015 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_24_NUM(val) vBIT(val, 3, 5)
6016 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_25_NUM(val) vBIT(val, 11, 5)
6017 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_26_NUM(val) vBIT(val, 19, 5)
6018 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_27_NUM(val) vBIT(val, 27, 5)
6019 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_28_NUM(val) vBIT(val, 35, 5)
6020 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_29_NUM(val) vBIT(val, 43, 5)
6021 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_30_NUM(val) vBIT(val, 51, 5)
6022 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_31_NUM(val) vBIT(val, 59, 5)
6024 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_32_NUM(val) vBIT(val, 3, 5)
6025 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_33_NUM(val) vBIT(val, 11, 5)
6026 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_34_NUM(val) vBIT(val, 19, 5)
6027 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_35_NUM(val) vBIT(val, 27, 5)
6028 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_36_NUM(val) vBIT(val, 35, 5)
6029 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_37_NUM(val) vBIT(val, 43, 5)
6030 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_38_NUM(val) vBIT(val, 51, 5)
6031 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_39_NUM(val) vBIT(val, 59, 5)
6033 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_40_NUM(val) vBIT(val, 3, 5)
6034 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_41_NUM(val) vBIT(val, 11, 5)
6035 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_42_NUM(val) vBIT(val, 19, 5)
6036 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_43_NUM(val) vBIT(val, 27, 5)
6037 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_44_NUM(val) vBIT(val, 35, 5)
6038 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_45_NUM(val) vBIT(val, 43, 5)
6039 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_46_NUM(val) vBIT(val, 51, 5)
6040 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_47_NUM(val) vBIT(val, 59, 5)
6042 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_48_NUM(val) vBIT(val, 3, 5)
6043 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_49_NUM(val) vBIT(val, 11, 5)
6044 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_50_NUM(val) vBIT(val, 19, 5)
6045 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_51_NUM(val) vBIT(val, 27, 5)
6046 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_52_NUM(val) vBIT(val, 35, 5)
6047 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_53_NUM(val) vBIT(val, 43, 5)
6048 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_54_NUM(val) vBIT(val, 51, 5)
6049 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_55_NUM(val) vBIT(val, 59, 5)
6051 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_56_NUM(val) vBIT(val, 3, 5)
6052 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_57_NUM(val) vBIT(val, 11, 5)
6053 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_58_NUM(val) vBIT(val, 19, 5)
6054 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_59_NUM(val) vBIT(val, 27, 5)
6055 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_60_NUM(val) vBIT(val, 35, 5)
6056 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_61_NUM(val) vBIT(val, 43, 5)
6057 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_62_NUM(val) vBIT(val, 51, 5)
6058 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_63_NUM(val) vBIT(val, 59, 5)
6060 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_64_NUM(val) vBIT(val, 3, 5)
6061 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_65_NUM(val) vBIT(val, 11, 5)
6062 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_66_NUM(val) vBIT(val, 19, 5)
6063 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_67_NUM(val) vBIT(val, 27, 5)
6064 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_68_NUM(val) vBIT(val, 35, 5)
6065 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_69_NUM(val) vBIT(val, 43, 5)
6066 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_70_NUM(val) vBIT(val, 51, 5)
6067 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_71_NUM(val) vBIT(val, 59, 5)
6069 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_72_NUM(val) vBIT(val, 3, 5)
6070 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_73_NUM(val) vBIT(val, 11, 5)
6071 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_74_NUM(val) vBIT(val, 19, 5)
6072 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_75_NUM(val) vBIT(val, 27, 5)
6073 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_76_NUM(val) vBIT(val, 35, 5)
6074 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_77_NUM(val) vBIT(val, 43, 5)
6075 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_78_NUM(val) vBIT(val, 51, 5)
6076 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_79_NUM(val) vBIT(val, 59, 5)
6078 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_80_NUM(val) vBIT(val, 3, 5)
6079 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_81_NUM(val) vBIT(val, 11, 5)
6080 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_82_NUM(val) vBIT(val, 19, 5)
6081 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_83_NUM(val) vBIT(val, 27, 5)
6082 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_84_NUM(val) vBIT(val, 35, 5)
6083 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_85_NUM(val) vBIT(val, 43, 5)
6084 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_86_NUM(val) vBIT(val, 51, 5)
6085 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_87_NUM(val) vBIT(val, 59, 5)
6087 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_88_NUM(val) vBIT(val, 3, 5)
6088 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_89_NUM(val) vBIT(val, 11, 5)
6089 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_90_NUM(val) vBIT(val, 19, 5)
6090 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_91_NUM(val) vBIT(val, 27, 5)
6091 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_92_NUM(val) vBIT(val, 35, 5)
6092 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_93_NUM(val) vBIT(val, 43, 5)
6093 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_94_NUM(val) vBIT(val, 51, 5)
6094 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_95_NUM(val) vBIT(val, 59, 5)
6096 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_96_NUM(val) vBIT(val, 3, 5)
6097 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_97_NUM(val) vBIT(val, 11, 5)
6098 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_98_NUM(val) vBIT(val, 19, 5)
6099 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_99_NUM(val) vBIT(val, 27, 5)
6100 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_100_NUM(val) vBIT(val, 35, 5)
6101 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_101_NUM(val) vBIT(val, 43, 5)
6102 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_102_NUM(val) vBIT(val, 51, 5)
6103 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_103_NUM(val) vBIT(val, 59, 5)
6105 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_104_NUM(val) vBIT(val, 3, 5)
6106 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_105_NUM(val) vBIT(val, 11, 5)
6107 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_106_NUM(val) vBIT(val, 19, 5)
6108 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_107_NUM(val) vBIT(val, 27, 5)
6109 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_108_NUM(val) vBIT(val, 35, 5)
6110 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_109_NUM(val) vBIT(val, 43, 5)
6111 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_110_NUM(val) vBIT(val, 51, 5)
6112 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_111_NUM(val) vBIT(val, 59, 5)
6114 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_112_NUM(val) vBIT(val, 3, 5)
6115 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_113_NUM(val) vBIT(val, 11, 5)
6116 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_114_NUM(val) vBIT(val, 19, 5)
6117 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_115_NUM(val) vBIT(val, 27, 5)
6118 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_116_NUM(val) vBIT(val, 35, 5)
6119 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_117_NUM(val) vBIT(val, 43, 5)
6120 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_118_NUM(val) vBIT(val, 51, 5)
6121 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_119_NUM(val) vBIT(val, 59, 5)
6123 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_120_NUM(val) vBIT(val, 3, 5)
6124 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_121_NUM(val) vBIT(val, 11, 5)
6125 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_122_NUM(val) vBIT(val, 19, 5)
6126 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_123_NUM(val) vBIT(val, 27, 5)
6127 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_124_NUM(val) vBIT(val, 35, 5)
6128 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_125_NUM(val) vBIT(val, 43, 5)
6129 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_126_NUM(val) vBIT(val, 51, 5)
6130 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_127_NUM(val) vBIT(val, 59, 5)
6132 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_128_NUM(val) vBIT(val, 3, 5)
6133 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_129_NUM(val) vBIT(val, 11, 5)
6134 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_130_NUM(val) vBIT(val, 19, 5)
6135 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_131_NUM(val) vBIT(val, 27, 5)
6136 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_132_NUM(val) vBIT(val, 35, 5)
6137 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_133_NUM(val) vBIT(val, 43, 5)
6138 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_134_NUM(val) vBIT(val, 51, 5)
6139 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_135_NUM(val) vBIT(val, 59, 5)
6141 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_136_NUM(val) vBIT(val, 3, 5)
6142 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_137_NUM(val) vBIT(val, 11, 5)
6143 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_138_NUM(val) vBIT(val, 19, 5)
6144 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_139_NUM(val) vBIT(val, 27, 5)
6145 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_140_NUM(val) vBIT(val, 35, 5)
6146 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_141_NUM(val) vBIT(val, 43, 5)
6147 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_142_NUM(val) vBIT(val, 51, 5)
6148 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_143_NUM(val) vBIT(val, 59, 5)
6150 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_144_NUM(val) vBIT(val, 3, 5)
6151 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_145_NUM(val) vBIT(val, 11, 5)
6152 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_146_NUM(val) vBIT(val, 19, 5)
6153 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_147_NUM(val) vBIT(val, 27, 5)
6154 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_148_NUM(val) vBIT(val, 35, 5)
6155 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_149_NUM(val) vBIT(val, 43, 5)
6156 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_150_NUM(val) vBIT(val, 51, 5)
6157 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_151_NUM(val) vBIT(val, 59, 5)
6159 #define VXGE_HAL_DBLGEN_WRR_CFG20_CTRL_SS_152_NUM(val) vBIT(val, 3, 5)
6161 #define VXGE_HAL_DEBUG_CFG1_TAG_TO_OBSERVE(val) vBIT(val, 3, 5)
6174 #define VXGE_HAL_TEST_CFG2_PERR_TIMEOUT_VAL(val) vBIT(val, 0, 32)
6178 #define VXGE_HAL_WRCRDTARB_CFG0_WAIT_CNT(val) vBIT(val, 48, 4)
6185 #define VXGE_HAL_WRCRDTARB_CFG2_STATS_PRTY_TIMEOUT_VAL(val) vBIT(val, 0, 32)
6186 #define VXGE_HAL_WRCRDTARB_CFG2_STATS_DROP_TIMEOUT_VAL(val) vBIT(val, 32, 32)
6188 #define VXGE_HAL_TEST_WRCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT1_VAL(val)\
6189 vBIT(val, 0, 32)
6190 #define VXGE_HAL_TEST_WRCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT2_VAL(val)\
6191 vBIT(val, 32, 32)
6193 #define VXGE_HAL_TEST_WRCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT3_VAL(val)\
6194 vBIT(val, 0, 32)
6195 #define VXGE_HAL_TEST_WRCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT4_VAL(val)\
6196 vBIT(val, 32, 32)
6198 #define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT1_MAP(val) vBIT(val, 3, 5)
6199 #define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT2_MAP(val) vBIT(val, 11, 5)
6200 #define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT3_MAP(val) vBIT(val, 19, 5)
6201 #define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT4_MAP(val) vBIT(val, 27, 5)
6208 #define VXGE_HAL_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS(val) vBIT(val, 18, 6)
6209 #define VXGE_HAL_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS(val) vBIT(val, 26, 6)
6210 #define VXGE_HAL_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS(val) vBIT(val, 34, 6)
6211 #define VXGE_HAL_RDCRDTARB_CFG0_WAIT_CNT(val) vBIT(val, 48, 4)
6212 #define VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val) vBIT(val, 54, 6)
6217 #define VXGE_HAL_RDCRDTARB_CFG2_SOFTNAK_TIMER_VAL_DIV4(val) vBIT(val, 0, 32)
6219 #define VXGE_HAL_TEST_RDCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT1_VAL(val)\
6220 vBIT(val, 0, 32)
6221 #define VXGE_HAL_TEST_RDCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT2_VAL(val)\
6222 vBIT(val, 32, 32)
6224 #define VXGE_HAL_TEST_RDCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT3_VAL(val)\
6225 vBIT(val, 0, 32)
6226 #define VXGE_HAL_TEST_RDCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT4_VAL(val)\
6227 vBIT(val, 32, 32)
6229 #define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT1_MAP(val) vBIT(val, 3, 5)
6230 #define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT2_MAP(val) vBIT(val, 11, 5)
6231 #define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT3_MAP(val) vBIT(val, 19, 5)
6232 #define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT4_MAP(val) vBIT(val, 27, 5)
6239 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_CLKA_SEL(val) vBIT(val, 0, 4)
6240 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_CLKB_SEL(val) vBIT(val, 4, 4)
6241 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_DA_SEL(val) vBIT(val, 10, 6)
6242 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_DB_SEL(val) vBIT(val, 18, 6)
6243 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBGA_SEL(val) vBIT(val, 28, 4)
6244 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBGB_SEL(val) vBIT(val, 32, 4)
6248 #define VXGE_HAL_SPI_CONTROL_3_REG_SECTOR_0_WR_EN(val) vBIT(val, 0, 32)
6259 #define VXGE_HAL_VECTOR_SRPCIM_ALARM_MAP_VECTOR_SRPCIM_ALARM_MAP(val)\
6260 vBIT(val, 17, 7)
6264 #define VXGE_HAL_VPLANE_RDCRDTARB_CFG0_TAGS_THRESHOLD_XOFF(val)\
6265 vBIT(val, 27, 5)
6266 #define VXGE_HAL_VPLANE_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val)\
6267 vBIT(val, 34, 6)
6271 #define VXGE_HAL_MRPCIM_SPI_CONTROL_KEY(val) vBIT(val, 0, 4)
6276 #define VXGE_HAL_MRPCIM_SPI_CONTROL_BYTE_CNT(val) vBIT(val, 29, 3)
6277 #define VXGE_HAL_MRPCIM_SPI_CONTROL_CMD(val) vBIT(val, 32, 8)
6278 #define VXGE_HAL_MRPCIM_SPI_CONTROL_ADD(val) vBIT(val, 40, 24)
6280 #define VXGE_HAL_MRPCIM_SPI_DATA_SPI_RWDATA(val) vBIT(val, 0, 64)
6289 #define VXGE_HAL_CHIP_FULL_RESET_CHIP_FULL_RESET(val) vBIT(val, 0, 8)
6291 #define VXGE_HAL_BF_SW_RESET_BF_SW_RESET(val) vBIT(val, 0, 8)
6299 #define VXGE_HAL_SW_RESET_CFG1_WAIT_TIME_FOR_FLUSH_PCI(val) vBIT(val, 7, 25)
6300 #define VXGE_HAL_SW_RESET_CFG1_SOPR_ASSERT_TIME(val) vBIT(val, 32, 4)
6301 #define VXGE_HAL_SW_RESET_CFG1_WAIT_TIME_AFTER_RESET(val) vBIT(val, 38, 25)
6304 #define VXGE_HAL_RIC_TIMEOUT_VAL(val) vBIT(val, 32, 32)
6306 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vBIT(val, 4, 10)
6307 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_VPLANE(val) vBIT(val, 19, 5)
6308 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_FUNC(val) vBIT(val, 27, 5)
6314 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_STATUS_DATA(val) vBIT(val, 32, 32)
6318 #define VXGE_HAL_RDCRDTARB_STATUS0_VPLANE_RDCRDTARB_ABS_AVAIL_NP_H(val)\
6319 vBIT(val, 0, 8)
6321 #define VXGE_HAL_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val) vBIT(val, 0, 32)
6322 #define VXGE_HAL_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val) vBIT(val, 32, 32)
6324 #define VXGE_HAL_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(val)\
6325 vBIT(val, 32, 32)
6327 #define VXGE_HAL_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(val)\
6328 vBIT(val, 32, 32)
6330 #define VXGE_HAL_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(val)\
6331 vBIT(val, 32, 32)
6333 #define VXGE_HAL_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val) vBIT(val, 0, 32)
6334 #define VXGE_HAL_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP(val) vBIT(val, 32, 32)
6336 #define VXGE_HAL_GENSTATS_COUNT01_GENSTATS_COUNT1(val) vBIT(val, 0, 32)
6337 #define VXGE_HAL_GENSTATS_COUNT01_GENSTATS_COUNT0(val) vBIT(val, 32, 32)
6339 #define VXGE_HAL_GENSTATS_COUNT23_GENSTATS_COUNT3(val) vBIT(val, 0, 32)
6340 #define VXGE_HAL_GENSTATS_COUNT23_GENSTATS_COUNT2(val) vBIT(val, 32, 32)
6342 #define VXGE_HAL_GENSTATS_COUNT4_GENSTATS_COUNT4(val) vBIT(val, 32, 32)
6344 #define VXGE_HAL_GENSTATS_COUNT5_GENSTATS_COUNT5(val) vBIT(val, 32, 32)
6346 #define VXGE_HAL_MRPCIM_MMIO_CFG1_WRITE_DATA(val) vBIT(val, 0, 32)
6347 #define VXGE_HAL_MRPCIM_MMIO_CFG1_ADDRESS(val) vBIT(val, 34, 6)
6348 #define VXGE_HAL_MRPCIM_MMIO_CFG1_MRIOVCTL_READ_DATA(val) vBIT(val, 48, 16)
6352 #define VXGE_HAL_GENSTATS_CFG_DTYPE_SEL(val) vBIT(val, 3, 5)
6353 #define VXGE_HAL_GENSTATS_CFG_CLIENT_NO_SEL(val) vBIT(val, 9, 3)
6354 #define VXGE_HAL_GENSTATS_CFG_WR_RD_CPL_SEL(val) vBIT(val, 14, 2)
6355 #define VXGE_HAL_GENSTATS_CFG_VPATH_SEL(val) vBIT(val, 31, 17)
6360 #define VXGE_HAL_PLL_SLIP_COUNTERS_CMG(val) vBIT(val, 0, 16)
6361 #define VXGE_HAL_PLL_SLIP_COUNTERS_FB(val) vBIT(val, 16, 16)
6362 #define VXGE_HAL_PLL_SLIP_COUNTERS_X(val) vBIT(val, 32, 16)
6375 #define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CACHE_DB_ERR(val) vBIT(val, 0, 3)
6376 #define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CMRSP_DB_ERR(val) vBIT(val, 3, 5)
6377 #define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE0_DB_ERR(val) vBIT(val, 8, 4)
6378 #define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE1_DB_ERR(val) vBIT(val, 12, 4)
6379 #define VXGE_HAL_GSTC_ERR0_REG_STC_H2L_EVENT_DB_ERR(val) vBIT(val, 16, 5)
6380 #define VXGE_HAL_GSTC_ERR0_REG_STC_PRM_EVENT_DB_ERR(val) vBIT(val, 21, 3)
6381 #define VXGE_HAL_GSTC_ERR0_REG_STC_SRCH_MEM_DB_ERR(val) vBIT(val, 24, 2)
6383 #define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CACHE_SG_ERR(val) vBIT(val, 32, 3)
6384 #define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CMRSP_SG_ERR(val) vBIT(val, 35, 5)
6385 #define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE0_SG_ERR(val) vBIT(val, 40, 4)
6386 #define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE1_SG_ERR(val) vBIT(val, 44, 4)
6387 #define VXGE_HAL_GSTC_ERR0_REG_STC_H2L_EVENT_SG_ERR(val) vBIT(val, 48, 5)
6388 #define VXGE_HAL_GSTC_ERR0_REG_STC_PRM_EVENT_SG_ERR(val) vBIT(val, 53, 3)
6389 #define VXGE_HAL_GSTC_ERR0_REG_STC_SRCH_MEM_SG_ERR(val) vBIT(val, 56, 2)
6438 #define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_DATX_DB_ERR(val) vBIT(val, 0, 2)
6439 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL0_DB_ERR(val) vBIT(val, 2, 2)
6440 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL1_DB_ERR(val) vBIT(val, 4, 2)
6441 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRBUF_DB_ERR(val) vBIT(val, 6, 2)
6443 #define VXGE_HAL_GH2L_ERR0_REG_H2L_CMCRSP_DB_ERR(val) vBIT(val, 9, 4)
6444 #define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_HEAD_DB_ERR(val) vBIT(val, 13, 2)
6447 #define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_DATX_SG_ERR(val) vBIT(val, 32, 2)
6448 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL0_SG_ERR(val) vBIT(val, 34, 2)
6449 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL1_SG_ERR(val) vBIT(val, 36, 2)
6450 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRBUF_SG_ERR(val) vBIT(val, 38, 2)
6451 #define VXGE_HAL_GH2L_ERR0_REG_H2L_CMCRSP_SG_ERR(val) vBIT(val, 41, 4)
6452 #define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_HEAD_SG_ERR(val) vBIT(val, 45, 2)
6532 #define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW0_SG_ERR(val) vBIT(val, 0, 4)
6533 #define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW0_DB_ERR(val) vBIT(val, 4, 4)
6534 #define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW1_SG_ERR(val) vBIT(val, 8, 4)
6535 #define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW1_DB_ERR(val) vBIT(val, 12, 4)
6543 #define VXGE_HAL_GSTC_CFG0_SCC_NBR_FREE_SLOTS(val) vBIT(val, 18, 6)
6544 #define VXGE_HAL_GSTC_CFG0_STC_LEFT_HASH_INDEX(val) vBIT(val, 27, 5)
6545 #define VXGE_HAL_GSTC_CFG0_STC_RIGHT_HASH_INDEX(val) vBIT(val, 35, 5)
6551 #define VXGE_HAL_GSTC_CFG1_INDIRECT_MODE(val) vBIT(val, 0, 17)
6552 #define VXGE_HAL_GSTC_CFG1_RPE_PF_COUNTDOWN(val) vBIT(val, 36, 12)
6553 #define VXGE_HAL_GSTC_CFG1_BDM_RATE_CTRL(val) vBIT(val, 54, 2)
6556 #define VXGE_HAL_GSTC_CFG2_MAX_FRE_CMREQ_ENTRIES(val) vBIT(val, 5, 3)
6571 #define VXGE_HAL_GSTC_CFG2_GPSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 36, 4)
6573 #define VXGE_HAL_STC_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2)
6574 #define VXGE_HAL_STC_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2)
6575 #define VXGE_HAL_STC_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2)
6576 #define VXGE_HAL_STC_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2)
6577 #define VXGE_HAL_STC_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2)
6578 #define VXGE_HAL_STC_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2)
6579 #define VXGE_HAL_STC_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2)
6580 #define VXGE_HAL_STC_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2)
6582 #define VXGE_HAL_STC_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2)
6583 #define VXGE_HAL_STC_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2)
6584 #define VXGE_HAL_STC_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2)
6585 #define VXGE_HAL_STC_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2)
6587 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L0_EVENTS(val) vBIT(val, 4, 4)
6588 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L1_EVENTS(val) vBIT(val, 12, 4)
6589 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L2_EVENTS(val) vBIT(val, 20, 4)
6590 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L3_EVENTS(val) vBIT(val, 28, 4)
6591 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_RPE_EVENTS(val) vBIT(val, 35, 5)
6592 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_MR_EVENTS(val) vBIT(val, 45, 3)
6594 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L0_FETCHES(val) vBIT(val, 5, 3)
6595 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L1_FETCHES(val) vBIT(val, 13, 3)
6596 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L2_FETCHES(val) vBIT(val, 21, 3)
6597 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L3_FETCHES(val) vBIT(val, 29, 3)
6598 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_RPE_FETCHES(val) vBIT(val, 37, 3)
6599 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_RPE_PF_FETCHES(val) vBIT(val, 46, 2)
6601 #define VXGE_HAL_STC_JHASH_CFG_GOLDEN(val) vBIT(val, 0, 32)
6602 #define VXGE_HAL_STC_JHASH_CFG_INIT_VAL(val) vBIT(val, 32, 32)
6604 #define VXGE_HAL_STC_SMI_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2)
6605 #define VXGE_HAL_STC_SMI_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2)
6606 #define VXGE_HAL_STC_SMI_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2)
6607 #define VXGE_HAL_STC_SMI_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2)
6608 #define VXGE_HAL_STC_SMI_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2)
6609 #define VXGE_HAL_STC_SMI_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2)
6610 #define VXGE_HAL_STC_SMI_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2)
6611 #define VXGE_HAL_STC_SMI_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2)
6613 #define VXGE_HAL_STC_SMI_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2)
6614 #define VXGE_HAL_STC_SMI_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2)
6615 #define VXGE_HAL_STC_SMI_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2)
6616 #define VXGE_HAL_STC_SMI_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2)
6617 #define VXGE_HAL_STC_SMI_ARB_CFG1_CAL9_PRI(val) vBIT(val, 38, 2)
6620 #define VXGE_HAL_STC_CAA_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2)
6621 #define VXGE_HAL_STC_CAA_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2)
6622 #define VXGE_HAL_STC_CAA_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2)
6623 #define VXGE_HAL_STC_CAA_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2)
6624 #define VXGE_HAL_STC_CAA_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2)
6625 #define VXGE_HAL_STC_CAA_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2)
6626 #define VXGE_HAL_STC_CAA_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2)
6627 #define VXGE_HAL_STC_CAA_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2)
6629 #define VXGE_HAL_STC_CAA_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2)
6630 #define VXGE_HAL_STC_CAA_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2)
6631 #define VXGE_HAL_STC_CAA_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2)
6632 #define VXGE_HAL_STC_CAA_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2)
6635 #define VXGE_HAL_STC_ECI_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2)
6636 #define VXGE_HAL_STC_ECI_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2)
6637 #define VXGE_HAL_STC_ECI_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2)
6638 #define VXGE_HAL_STC_ECI_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2)
6639 #define VXGE_HAL_STC_ECI_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2)
6640 #define VXGE_HAL_STC_ECI_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2)
6641 #define VXGE_HAL_STC_ECI_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2)
6642 #define VXGE_HAL_STC_ECI_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2)
6644 #define VXGE_HAL_STC_ECI_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2)
6645 #define VXGE_HAL_STC_ECI_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2)
6646 #define VXGE_HAL_STC_ECI_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2)
6647 #define VXGE_HAL_STC_ECI_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2)
6663 #define VXGE_HAL_STC_ECI_CFG0_RESUBMIT_INTERVAL(val) vBIT(val, 40, 8)
6705 #define VXGE_HAL_H2L_MISC_CFG_HOCHEAD_RD_THRES(val) vBIT(val, 10, 6)
6706 #define VXGE_HAL_H2L_MISC_CFG_HCC_WB_THRESHOLD(val) vBIT(val, 19, 5)
6707 #define VXGE_HAL_H2L_MISC_CFG_HOP_BCK_STATS_MODE(val) vBIT(val, 25, 2)
6708 #define VXGE_HAL_H2L_MISC_CFG_HOP_BCK_STATS_VPATH(val) vBIT(val, 27, 5)
6717 #define VXGE_HAL_HSQ_CFG_BASE_ADDR(val) vBIT(val, 8, 24)
6718 #define VXGE_HAL_HSQ_CFG_SIZE224(val) vBIT(val, 40, 24)
6720 #define VXGE_HAL_USDC_VPBP_CFG_THRES224(val) vBIT(val, 8, 24)
6721 #define VXGE_HAL_USDC_VPBP_CFG_HYST224(val) vBIT(val, 40, 24)
6723 #define VXGE_HAL_KDFC_VPBP_CFG_THRES224(val) vBIT(val, 8, 24)
6724 #define VXGE_HAL_KDFC_VPBP_CFG_HYST224(val) vBIT(val, 40, 24)
6726 #define VXGE_HAL_TXPE_VPBP_CFG_THRES224(val) vBIT(val, 8, 24)
6727 #define VXGE_HAL_TXPE_VPBP_CFG_HYST224(val) vBIT(val, 40, 24)
6729 #define VXGE_HAL_ONE_VPBP_CFG_THRES224(val) vBIT(val, 8, 24)
6730 #define VXGE_HAL_ONE_VPBP_CFG_HYST224(val) vBIT(val, 40, 24)
6732 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_0_NUM(val) vBIT(val, 3, 5)
6733 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_1_NUM(val) vBIT(val, 11, 5)
6734 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_2_NUM(val) vBIT(val, 19, 5)
6735 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_3_NUM(val) vBIT(val, 27, 5)
6736 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_4_NUM(val) vBIT(val, 35, 5)
6737 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_5_NUM(val) vBIT(val, 43, 5)
6738 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_6_NUM(val) vBIT(val, 51, 5)
6739 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_7_NUM(val) vBIT(val, 59, 5)
6741 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_8_NUM(val) vBIT(val, 3, 5)
6742 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_9_NUM(val) vBIT(val, 11, 5)
6743 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_10_NUM(val) vBIT(val, 19, 5)
6744 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_11_NUM(val) vBIT(val, 27, 5)
6745 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_12_NUM(val) vBIT(val, 35, 5)
6746 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_13_NUM(val) vBIT(val, 43, 5)
6747 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_14_NUM(val) vBIT(val, 51, 5)
6748 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_15_NUM(val) vBIT(val, 59, 5)
6750 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_16_NUM(val) vBIT(val, 3, 5)
6751 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_17_NUM(val) vBIT(val, 11, 5)
6752 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_18_NUM(val) vBIT(val, 19, 5)
6753 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_19_NUM(val) vBIT(val, 27, 5)
6754 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_20_NUM(val) vBIT(val, 35, 5)
6755 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_21_NUM(val) vBIT(val, 43, 5)
6756 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_22_NUM(val) vBIT(val, 51, 5)
6757 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_23_NUM(val) vBIT(val, 59, 5)
6759 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_24_NUM(val) vBIT(val, 3, 5)
6760 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_25_NUM(val) vBIT(val, 11, 5)
6761 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_26_NUM(val) vBIT(val, 19, 5)
6762 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_27_NUM(val) vBIT(val, 27, 5)
6763 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_28_NUM(val) vBIT(val, 35, 5)
6764 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_29_NUM(val) vBIT(val, 43, 5)
6765 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_30_NUM(val) vBIT(val, 51, 5)
6766 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_31_NUM(val) vBIT(val, 59, 5)
6768 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_32_NUM(val) vBIT(val, 3, 5)
6769 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_33_NUM(val) vBIT(val, 11, 5)
6770 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_34_NUM(val) vBIT(val, 19, 5)
6771 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_35_NUM(val) vBIT(val, 27, 5)
6772 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_36_NUM(val) vBIT(val, 35, 5)
6773 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_37_NUM(val) vBIT(val, 43, 5)
6774 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_38_NUM(val) vBIT(val, 51, 5)
6775 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_39_NUM(val) vBIT(val, 59, 5)
6777 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_40_NUM(val) vBIT(val, 3, 5)
6778 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_41_NUM(val) vBIT(val, 11, 5)
6779 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_42_NUM(val) vBIT(val, 19, 5)
6780 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_43_NUM(val) vBIT(val, 27, 5)
6781 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_44_NUM(val) vBIT(val, 35, 5)
6782 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_45_NUM(val) vBIT(val, 43, 5)
6783 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_46_NUM(val) vBIT(val, 51, 5)
6784 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_47_NUM(val) vBIT(val, 59, 5)
6786 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_48_NUM(val) vBIT(val, 3, 5)
6787 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_49_NUM(val) vBIT(val, 11, 5)
6788 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_50_NUM(val) vBIT(val, 19, 5)
6789 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_51_NUM(val) vBIT(val, 27, 5)
6790 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_52_NUM(val) vBIT(val, 35, 5)
6791 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_53_NUM(val) vBIT(val, 43, 5)
6792 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_54_NUM(val) vBIT(val, 51, 5)
6793 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_55_NUM(val) vBIT(val, 59, 5)
6795 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_56_NUM(val) vBIT(val, 3, 5)
6796 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_57_NUM(val) vBIT(val, 11, 5)
6797 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_58_NUM(val) vBIT(val, 19, 5)
6798 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_59_NUM(val) vBIT(val, 27, 5)
6799 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_60_NUM(val) vBIT(val, 35, 5)
6800 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_61_NUM(val) vBIT(val, 43, 5)
6801 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_62_NUM(val) vBIT(val, 51, 5)
6802 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_63_NUM(val) vBIT(val, 59, 5)
6804 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_64_NUM(val) vBIT(val, 3, 5)
6805 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_65_NUM(val) vBIT(val, 11, 5)
6806 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_66_NUM(val) vBIT(val, 19, 5)
6807 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_67_NUM(val) vBIT(val, 27, 5)
6808 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_68_NUM(val) vBIT(val, 35, 5)
6809 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_69_NUM(val) vBIT(val, 43, 5)
6810 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_70_NUM(val) vBIT(val, 51, 5)
6811 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_71_NUM(val) vBIT(val, 59, 5)
6813 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_72_NUM(val) vBIT(val, 3, 5)
6814 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_73_NUM(val) vBIT(val, 11, 5)
6815 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_74_NUM(val) vBIT(val, 19, 5)
6816 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_75_NUM(val) vBIT(val, 27, 5)
6817 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_76_NUM(val) vBIT(val, 35, 5)
6818 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_77_NUM(val) vBIT(val, 43, 5)
6819 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_78_NUM(val) vBIT(val, 51, 5)
6820 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_79_NUM(val) vBIT(val, 59, 5)
6822 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_80_NUM(val) vBIT(val, 3, 5)
6823 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_81_NUM(val) vBIT(val, 11, 5)
6824 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_82_NUM(val) vBIT(val, 19, 5)
6825 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_83_NUM(val) vBIT(val, 27, 5)
6826 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_84_NUM(val) vBIT(val, 35, 5)
6827 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_85_NUM(val) vBIT(val, 43, 5)
6828 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_86_NUM(val) vBIT(val, 51, 5)
6829 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_87_NUM(val) vBIT(val, 59, 5)
6831 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_88_NUM(val) vBIT(val, 3, 5)
6832 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_89_NUM(val) vBIT(val, 11, 5)
6833 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_90_NUM(val) vBIT(val, 19, 5)
6834 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_91_NUM(val) vBIT(val, 27, 5)
6835 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_92_NUM(val) vBIT(val, 35, 5)
6836 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_93_NUM(val) vBIT(val, 43, 5)
6837 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_94_NUM(val) vBIT(val, 51, 5)
6838 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_95_NUM(val) vBIT(val, 59, 5)
6840 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_96_NUM(val) vBIT(val, 3, 5)
6841 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_97_NUM(val) vBIT(val, 11, 5)
6842 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_98_NUM(val) vBIT(val, 19, 5)
6843 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_99_NUM(val) vBIT(val, 27, 5)
6844 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_100_NUM(val) vBIT(val, 35, 5)
6845 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_101_NUM(val) vBIT(val, 43, 5)
6846 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_102_NUM(val) vBIT(val, 51, 5)
6847 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_103_NUM(val) vBIT(val, 59, 5)
6849 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_104_NUM(val) vBIT(val, 3, 5)
6850 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_105_NUM(val) vBIT(val, 11, 5)
6851 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_106_NUM(val) vBIT(val, 19, 5)
6852 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_107_NUM(val) vBIT(val, 27, 5)
6853 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_108_NUM(val) vBIT(val, 35, 5)
6854 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_109_NUM(val) vBIT(val, 43, 5)
6855 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_110_NUM(val) vBIT(val, 51, 5)
6856 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_111_NUM(val) vBIT(val, 59, 5)
6858 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_112_NUM(val) vBIT(val, 3, 5)
6859 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_113_NUM(val) vBIT(val, 11, 5)
6860 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_114_NUM(val) vBIT(val, 19, 5)
6861 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_115_NUM(val) vBIT(val, 27, 5)
6862 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_116_NUM(val) vBIT(val, 35, 5)
6863 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_117_NUM(val) vBIT(val, 43, 5)
6864 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_118_NUM(val) vBIT(val, 51, 5)
6865 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_119_NUM(val) vBIT(val, 59, 5)
6867 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_120_NUM(val) vBIT(val, 3, 5)
6868 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_121_NUM(val) vBIT(val, 11, 5)
6869 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_122_NUM(val) vBIT(val, 19, 5)
6870 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_123_NUM(val) vBIT(val, 27, 5)
6871 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_124_NUM(val) vBIT(val, 35, 5)
6872 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_125_NUM(val) vBIT(val, 43, 5)
6873 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_126_NUM(val) vBIT(val, 51, 5)
6874 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_127_NUM(val) vBIT(val, 59, 5)
6876 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_128_NUM(val) vBIT(val, 3, 5)
6877 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_129_NUM(val) vBIT(val, 11, 5)
6878 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_130_NUM(val) vBIT(val, 19, 5)
6879 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_131_NUM(val) vBIT(val, 27, 5)
6880 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_132_NUM(val) vBIT(val, 35, 5)
6881 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_133_NUM(val) vBIT(val, 43, 5)
6882 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_134_NUM(val) vBIT(val, 51, 5)
6883 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_135_NUM(val) vBIT(val, 59, 5)
6885 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_136_NUM(val) vBIT(val, 3, 5)
6886 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_137_NUM(val) vBIT(val, 11, 5)
6887 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_138_NUM(val) vBIT(val, 19, 5)
6888 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_139_NUM(val) vBIT(val, 27, 5)
6889 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_140_NUM(val) vBIT(val, 35, 5)
6890 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_141_NUM(val) vBIT(val, 43, 5)
6891 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_142_NUM(val) vBIT(val, 51, 5)
6892 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_143_NUM(val) vBIT(val, 59, 5)
6894 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_144_NUM(val) vBIT(val, 3, 5)
6895 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_145_NUM(val) vBIT(val, 11, 5)
6896 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_146_NUM(val) vBIT(val, 19, 5)
6897 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_147_NUM(val) vBIT(val, 27, 5)
6898 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_148_NUM(val) vBIT(val, 35, 5)
6899 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_149_NUM(val) vBIT(val, 43, 5)
6900 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_150_NUM(val) vBIT(val, 51, 5)
6901 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_151_NUM(val) vBIT(val, 59, 5)
6903 #define VXGE_HAL_HOPARB_WRR_CTRL_19_SS_152_NUM(val) vBIT(val, 3, 5)
6905 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP0_NUM(val) vBIT(val, 3, 5)
6906 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP1_NUM(val) vBIT(val, 11, 5)
6907 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP2_NUM(val) vBIT(val, 19, 5)
6908 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP3_NUM(val) vBIT(val, 27, 5)
6909 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP4_NUM(val) vBIT(val, 35, 5)
6910 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP5_NUM(val) vBIT(val, 43, 5)
6911 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP6_NUM(val) vBIT(val, 51, 5)
6912 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP7_NUM(val) vBIT(val, 59, 5)
6914 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP8_NUM(val) vBIT(val, 3, 5)
6915 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP9_NUM(val) vBIT(val, 11, 5)
6916 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP10_NUM(val) vBIT(val, 19, 5)
6917 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP11_NUM(val) vBIT(val, 27, 5)
6918 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP12_NUM(val) vBIT(val, 35, 5)
6919 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP13_NUM(val) vBIT(val, 43, 5)
6920 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP14_NUM(val) vBIT(val, 51, 5)
6921 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP15_NUM(val) vBIT(val, 59, 5)
6923 #define VXGE_HAL_HOPARB_WRR_CMP_2_VP16_NUM(val) vBIT(val, 3, 5)
6927 #define VXGE_HAL_HOP_BCK_STATS0_HO_DISPATCH_CNT(val) vBIT(val, 0, 32)
6928 #define VXGE_HAL_HOP_BCK_STATS0_HO_DROP_CNT(val) vBIT(val, 32, 32)
6973 #define VXGE_HAL_PH2L_ERR0_REG_H2L_PHDR_MEM_DB_ERR(val) vBIT(val, 8, 2)
6974 #define VXGE_HAL_PH2L_ERR0_REG_H2L_IDATA_MEM_DB_ERR(val) vBIT(val, 10, 2)
6975 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RO_CACHE_DB_ERR(val) vBIT(val, 12, 3)
7001 #define VXGE_HAL_PH2L_ERR0_REG_H2L_PHDR_MEM_SG_ERR(val) vBIT(val, 48, 2)
7002 #define VXGE_HAL_PH2L_ERR0_REG_H2L_IDATA_MEM_SG_ERR(val) vBIT(val, 50, 2)
7003 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RO_CACHE_SG_ERR(val) vBIT(val, 52, 3)
7009 #define VXGE_HAL_DAM_BYPASS_QUEUE_0_BASE(val) vBIT(val, 8, 24)
7010 #define VXGE_HAL_DAM_BYPASS_QUEUE_0_LENGTH(val) vBIT(val, 40, 24)
7012 #define VXGE_HAL_DAM_BYPASS_QUEUE_1_BASE(val) vBIT(val, 8, 24)
7013 #define VXGE_HAL_DAM_BYPASS_QUEUE_1_LENGTH(val) vBIT(val, 40, 24)
7015 #define VXGE_HAL_DAM_BYPASS_QUEUE_2_BASE(val) vBIT(val, 8, 24)
7016 #define VXGE_HAL_DAM_BYPASS_QUEUE_2_LENGTH(val) vBIT(val, 40, 24)
7026 #define VXGE_HAL_PH2L_CFG0_NBR_RETX_SLOTS_PER_VP(val) vBIT(val, 62, 2)
7031 #define VXGE_HAL_PSTC_CFG0_PGSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 12, 4)
7053 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_NMBC_ERROR(val) vBIT(val, 56, 4)
7055 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG1(val) vBIT(val, 0, 3)
7056 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG2(val) vBIT(val, 3, 3)
7057 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG3(val) vBIT(val, 6, 3)
7058 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_DRBELL(val) vBIT(val, 9, 3)
7059 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_FBif (val) vBIT(val, 12, 3)
7060 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_MSG(val) vBIT(val, 15, 3)
7061 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_ONE(val) vBIT(val, 18, 3)
7062 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_PCI(val) vBIT(val, 21, 3)
7063 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_RTDMA(val) vBIT(val, 24, 3)
7064 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_WRDMA(val) vBIT(val, 27, 3)
7065 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_XGMAC(val) vBIT(val, 30, 3)
7069 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7070 vBIT(val, 0, 2)
7071 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\
7072 vBIT(val, 2, 8)
7073 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
7074 vBIT(val, 10, 2)
7075 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\
7076 vBIT(val, 12, 8)
7077 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
7078 vBIT(val, 20, 2)
7080 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7081 vBIT(val, 0, 2)
7082 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\
7083 vBIT(val, 2, 8)
7084 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
7085 vBIT(val, 10, 2)
7086 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\
7087 vBIT(val, 12, 8)
7088 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
7089 vBIT(val, 20, 2)
7091 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7092 vBIT(val, 0, 2)
7093 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\
7094 vBIT(val, 2, 8)
7095 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
7096 vBIT(val, 10, 2)
7097 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\
7098 vBIT(val, 12, 8)
7099 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
7100 vBIT(val, 20, 2)
7102 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7103 vBIT(val, 0, 2)
7104 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\
7105 vBIT(val, 2, 8)
7106 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
7107 vBIT(val, 10, 2)
7108 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\
7109 vBIT(val, 12, 8)
7110 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
7111 vBIT(val, 20, 2)
7113 #define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7114 vBIT(val, 0, 2)
7115 #define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\
7116 vBIT(val, 2, 8)
7118 #define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7119 vBIT(val, 0, 2)
7120 #define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\
7121 vBIT(val, 2, 8)
7123 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7124 vBIT(val, 0, 2)
7125 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\
7126 vBIT(val, 2, 7)
7127 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
7128 vBIT(val, 9, 3)
7129 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\
7130 vBIT(val, 12, 7)
7131 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
7132 vBIT(val, 19, 3)
7134 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7135 vBIT(val, 0, 2)
7136 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\
7137 vBIT(val, 2, 7)
7138 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
7139 vBIT(val, 9, 3)
7140 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\
7141 vBIT(val, 12, 7)
7142 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
7143 vBIT(val, 19, 3)
7145 #define VXGE_HAL_RF_CQM_DMACQERSP_RTL_TOP_CMG1_NMB_IO_REPAIR_STATUS(val)\
7146 vBIT(val, 0, 2)
7147 #define VXGE_HAL_RF_CQM_DMACQERSP_RTL_TOP_CMG1_NMB_IO_ALL_FUSE(val)\
7148 vBIT(val, 2, 8)
7150 #define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7151 vBIT(val, 0, 2)
7152 #define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\
7153 vBIT(val, 2, 8)
7155 #define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7156 vBIT(val, 0, 2)
7157 #define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\
7158 vBIT(val, 2, 8)
7160 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7161 vBIT(val, 0, 2)
7162 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_0_CMG1_NMB_IO_ALL_FUSE(val)\
7163 vBIT(val, 2, 7)
7165 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7166 vBIT(val, 0, 2)
7167 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_0_CMG1_NMB_IO_ALL_FUSE(val)\
7168 vBIT(val, 2, 7)
7170 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7171 vBIT(val, 0, 2)
7172 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_1_CMG1_NMB_IO_ALL_FUSE(val)\
7173 vBIT(val, 2, 7)
7175 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7176 vBIT(val, 0, 2)
7177 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_1_CMG1_NMB_IO_ALL_FUSE(val)\
7178 vBIT(val, 2, 7)
7180 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7181 vBIT(val, 0, 2)
7182 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
7183 vBIT(val, 2, 8)
7185 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7186 vBIT(val, 0, 2)
7187 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
7188 vBIT(val, 2, 8)
7190 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
7191 vBIT(val, 0, 2)
7192 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
7193 vBIT(val, 2, 8)
7195 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7196 vBIT(val, 0, 2)
7197 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
7198 vBIT(val, 2, 8)
7200 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7201 vBIT(val, 0, 2)
7202 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
7203 vBIT(val, 2, 8)
7205 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
7206 vBIT(val, 0, 2)
7207 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
7208 vBIT(val, 2, 8)
7210 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7211 vBIT(val, 0, 2)
7212 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
7213 vBIT(val, 2, 8)
7215 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7216 vBIT(val, 0, 2)
7217 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
7218 vBIT(val, 2, 8)
7220 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
7221 vBIT(val, 0, 2)
7222 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
7223 vBIT(val, 2, 8)
7225 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7226 vBIT(val, 0, 2)
7227 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
7228 vBIT(val, 2, 8)
7230 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7231 vBIT(val, 0, 2)
7232 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
7233 vBIT(val, 2, 8)
7235 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7236 vBIT(val, 0, 2)
7237 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
7238 vBIT(val, 2, 8)
7240 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
7241 vBIT(val, 0, 2)
7242 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
7243 vBIT(val, 2, 8)
7245 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7246 vBIT(val, 0, 2)
7247 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
7248 vBIT(val, 2, 8)
7250 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7251 vBIT(val, 0, 2)
7252 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
7253 vBIT(val, 2, 8)
7255 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7256 vBIT(val, 0, 2)
7257 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
7258 vBIT(val, 2, 8)
7260 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
7261 vBIT(val, 0, 2)
7262 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
7263 vBIT(val, 2, 8)
7265 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
7266 vBIT(val, 0, 2)
7267 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
7268 vBIT(val, 2, 8)
7270 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7271 vBIT(val, 0, 2)
7272 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
7273 vBIT(val, 2, 8)
7275 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7276 vBIT(val, 0, 2)
7277 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
7278 vBIT(val, 2, 8)
7280 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7281 vBIT(val, 0, 2)
7282 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
7283 vBIT(val, 2, 8)
7285 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7286 vBIT(val, 0, 2)
7287 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
7288 vBIT(val, 2, 8)
7290 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
7291 vBIT(val, 0, 2)
7292 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
7293 vBIT(val, 2, 8)
7295 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
7296 vBIT(val, 0, 2)
7297 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
7298 vBIT(val, 2, 8)
7300 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7301 vBIT(val, 0, 2)
7302 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
7303 vBIT(val, 2, 8)
7305 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7306 vBIT(val, 0, 2)
7307 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
7308 vBIT(val, 2, 8)
7310 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7311 vBIT(val, 0, 2)
7312 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
7313 vBIT(val, 2, 8)
7315 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7316 vBIT(val, 0, 2)
7317 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
7318 vBIT(val, 2, 8)
7320 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
7321 vBIT(val, 0, 2)
7322 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
7323 vBIT(val, 2, 8)
7325 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
7326 vBIT(val, 0, 2)
7327 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
7328 vBIT(val, 2, 8)
7330 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
7331 vBIT(val, 0, 2)
7332 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\
7333 vBIT(val, 2, 8)
7335 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
7336 vBIT(val, 0, 2)
7337 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\
7338 vBIT(val, 2, 8)
7340 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_2_CMG1_NMB_IO_REPAIR_STATUS(val)\
7341 vBIT(val, 0, 2)
7342 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_2_CMG1_NMB_IO_ALL_FUSE(val)\
7343 vBIT(val, 2, 8)
7345 #define VXGE_HAL_RF_UQM_CMCREQ_RTL_TOP_CMG1_NMB_IO_REPAIR_STATUS(val)\
7346 vBIT(val, 0, 2)
7347 #define VXGE_HAL_RF_UQM_CMCREQ_RTL_TOP_CMG1_NMB_IO_ALL_FUSE(val)\
7348 vBIT(val, 2, 8)
7350 #define VXGE_HAL_RR0_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
7351 vBIT(val, 0, 2)
7352 #define VXGE_HAL_RR0_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
7353 vBIT(val, 2, 8)
7355 #define VXGE_HAL_RR1_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
7356 vBIT(val, 0, 2)
7357 #define VXGE_HAL_RR1_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
7358 vBIT(val, 2, 8)
7360 #define VXGE_HAL_RR2_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
7361 vBIT(val, 0, 2)
7362 #define VXGE_HAL_RR2_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
7363 vBIT(val, 2, 8)
7365 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP0_CMG2_NMB_IO_REPAIR_STATUS(val)\
7366 vBIT(val, 0, 2)
7367 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP0_CMG2_NMB_IO_ALL_FUSE(val)\
7368 vBIT(val, 2, 8)
7370 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP1_CMG2_NMB_IO_REPAIR_STATUS(val)\
7371 vBIT(val, 0, 2)
7372 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP1_CMG2_NMB_IO_ALL_FUSE(val)\
7373 vBIT(val, 2, 8)
7375 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP2_CMG2_NMB_IO_REPAIR_STATUS(val)\
7376 vBIT(val, 0, 2)
7377 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP2_CMG2_NMB_IO_ALL_FUSE(val)\
7378 vBIT(val, 2, 8)
7380 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
7381 vBIT(val, 0, 2)
7382 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\
7383 vBIT(val, 2, 6)
7385 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
7386 vBIT(val, 0, 2)
7387 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\
7388 vBIT(val, 2, 6)
7390 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
7391 vBIT(val, 0, 2)
7392 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\
7393 vBIT(val, 2, 6)
7395 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
7396 vBIT(val, 0, 2)
7397 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\
7398 vBIT(val, 2, 6)
7400 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
7401 vBIT(val, 0, 2)
7402 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_0_CMG2_NMB_IO_ALL_FUSE(val)\
7403 vBIT(val, 2, 6)
7405 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
7406 vBIT(val, 0, 2)
7407 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_1_CMG2_NMB_IO_ALL_FUSE(val)\
7408 vBIT(val, 2, 6)
7410 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_2_CMG2_NMB_IO_REPAIR_STATUS(val)\
7411 vBIT(val, 0, 2)
7412 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_2_CMG2_NMB_IO_ALL_FUSE(val)\
7413 vBIT(val, 2, 6)
7415 #define VXGE_HAL_RF_CP_QCC2CXP_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
7416 vBIT(val, 0, 2)
7417 #define VXGE_HAL_RF_CP_QCC2CXP_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
7418 vBIT(val, 2, 7)
7420 #define VXGE_HAL_RF_CP_STC2CP_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
7421 vBIT(val, 0, 2)
7422 #define VXGE_HAL_RF_CP_STC2CP_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
7423 vBIT(val, 2, 8)
7425 #define VXGE_HAL_RF_CP_XT_TRACE_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
7426 vBIT(val, 0, 2)
7427 #define VXGE_HAL_RF_CP_XT_TRACE_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
7428 vBIT(val, 2, 8)
7430 #define VXGE_HAL_RF_CP_XT_DTAG_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
7431 vBIT(val, 0, 2)
7432 #define VXGE_HAL_RF_CP_XT_DTAG_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
7433 vBIT(val, 2, 6)
7435 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
7436 vBIT(val, 0, 2)
7437 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\
7438 vBIT(val, 2, 7)
7440 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
7441 vBIT(val, 0, 2)
7442 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\
7443 vBIT(val, 2, 7)
7445 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
7446 vBIT(val, 0, 2)
7447 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\
7448 vBIT(val, 2, 7)
7450 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
7451 vBIT(val, 0, 2)
7452 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\
7453 vBIT(val, 2, 7)
7455 #define VXGE_HAL_RF_CP_XT_ITAG_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
7456 vBIT(val, 0, 2)
7457 #define VXGE_HAL_RF_CP_XT_ITAG_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
7458 vBIT(val, 2, 6)
7460 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
7461 vBIT(val, 0, 2)
7462 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\
7463 vBIT(val, 2, 7)
7465 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
7466 vBIT(val, 0, 2)
7467 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\
7468 vBIT(val, 2, 7)
7470 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
7471 vBIT(val, 0, 2)
7472 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\
7473 vBIT(val, 2, 7)
7475 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
7476 vBIT(val, 0, 2)
7477 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\
7478 vBIT(val, 2, 7)
7480 #define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
7481 vBIT(val, 0, 2)
7482 #define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_0_CMG2_NMB_IO_ALL_FUSE(val)\
7483 vBIT(val, 2, 8)
7485 #define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
7486 vBIT(val, 0, 2)
7487 #define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_1_CMG2_NMB_IO_ALL_FUSE(val)\
7488 vBIT(val, 2, 8)
7490 #define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM0_CMG2_NMB_IO_REPAIR_STATUS(val)\
7491 vBIT(val, 0, 2)
7492 #define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM0_CMG2_NMB_IO_ALL_FUSE(val)\
7493 vBIT(val, 2, 8)
7495 #define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM1_CMG2_NMB_IO_REPAIR_STATUS(val)\
7496 vBIT(val, 0, 2)
7497 #define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM1_CMG2_NMB_IO_ALL_FUSE(val)\
7498 vBIT(val, 2, 8)
7500 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_0_CMG3_NMB_IO_REPAIR_STATUS(val)\
7501 vBIT(val, 0, 2)
7502 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_0_CMG3_NMB_IO_ALL_FUSE(val)\
7503 vBIT(val, 2, 8)
7505 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_0_CMG3_NMB_IO_REPAIR_STATUS(val)\
7506 vBIT(val, 0, 2)
7507 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_0_CMG3_NMB_IO_ALL_FUSE(val)\
7508 vBIT(val, 2, 8)
7510 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_1_CMG3_NMB_IO_REPAIR_STATUS(val)\
7511 vBIT(val, 0, 2)
7512 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_1_CMG3_NMB_IO_ALL_FUSE(val)\
7513 vBIT(val, 2, 8)
7515 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_1_CMG3_NMB_IO_REPAIR_STATUS(val)\
7516 vBIT(val, 0, 2)
7517 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_1_CMG3_NMB_IO_ALL_FUSE(val)\
7518 vBIT(val, 2, 8)
7520 #define VXGE_HAL_RF_DAM_WRRESP_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\
7521 vBIT(val, 0, 2)
7522 #define VXGE_HAL_RF_DAM_WRRESP_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\
7523 vBIT(val, 2, 6)
7525 #define VXGE_HAL_RF_DAM_RDSB_FIFO_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\
7526 vBIT(val, 0, 2)
7527 #define VXGE_HAL_RF_DAM_RDSB_FIFO_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\
7528 vBIT(val, 2, 7)
7530 #define VXGE_HAL_RF_DAM_WRSB_FIFO_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\
7531 vBIT(val, 0, 2)
7532 #define VXGE_HAL_RF_DAM_WRSB_FIFO_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\
7533 vBIT(val, 2, 7)
7535 #define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7536 vBIT(val, 0, 2)
7537 #define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
7538 vBIT(val, 2, 6)
7539 #define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
7540 vBIT(val, 8, 5)
7541 #define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
7542 vBIT(val, 13, 6)
7543 #define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
7544 vBIT(val, 19, 5)
7546 #define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7547 vBIT(val, 0, 2)
7548 #define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
7549 vBIT(val, 2, 6)
7550 #define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
7551 vBIT(val, 8, 5)
7552 #define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
7553 vBIT(val, 13, 6)
7554 #define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
7555 vBIT(val, 19, 5)
7557 #define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7558 vBIT(val, 0, 2)
7559 #define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
7560 vBIT(val, 2, 6)
7561 #define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
7562 vBIT(val, 8, 5)
7563 #define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
7564 vBIT(val, 13, 6)
7565 #define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
7566 vBIT(val, 19, 5)
7568 #define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7569 vBIT(val, 0, 2)
7570 #define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
7571 vBIT(val, 2, 6)
7572 #define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
7573 vBIT(val, 8, 5)
7574 #define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
7575 vBIT(val, 13, 6)
7576 #define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
7577 vBIT(val, 19, 5)
7579 #define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7580 vBIT(val, 0, 2)
7581 #define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
7582 vBIT(val, 2, 6)
7583 #define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
7584 vBIT(val, 8, 5)
7585 #define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
7586 vBIT(val, 13, 6)
7587 #define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
7588 vBIT(val, 19, 5)
7590 #define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7591 vBIT(val, 0, 2)
7592 #define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
7593 vBIT(val, 2, 6)
7594 #define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
7595 vBIT(val, 8, 5)
7596 #define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
7597 vBIT(val, 13, 6)
7598 #define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
7599 vBIT(val, 19, 5)
7601 #define VXGE_HAL_RF_USDC_0_FIFO_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7602 vBIT(val, 0, 2)
7603 #define VXGE_HAL_RF_USDC_0_FIFO_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
7604 vBIT(val, 2, 7)
7606 #define VXGE_HAL_RF_USDC_1_FIFO_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7607 vBIT(val, 0, 2)
7608 #define VXGE_HAL_RF_USDC_1_FIFO_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
7609 vBIT(val, 2, 7)
7611 #define VXGE_HAL_RF_USDC_0_WA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7612 vBIT(val, 0, 2)
7613 #define VXGE_HAL_RF_USDC_0_WA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
7614 vBIT(val, 2, 7)
7616 #define VXGE_HAL_RF_USDC_1_WA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7617 vBIT(val, 0, 2)
7618 #define VXGE_HAL_RF_USDC_1_WA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
7619 vBIT(val, 2, 7)
7621 #define VXGE_HAL_RF_USDC_0_SA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7622 vBIT(val, 0, 2)
7623 #define VXGE_HAL_RF_USDC_0_SA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
7624 vBIT(val, 2, 7)
7626 #define VXGE_HAL_RF_USDC_1_SA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7627 vBIT(val, 0, 2)
7628 #define VXGE_HAL_RF_USDC_1_SA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
7629 vBIT(val, 2, 7)
7631 #define VXGE_HAL_RF_USDC_0_CA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7632 vBIT(val, 0, 2)
7633 #define VXGE_HAL_RF_USDC_0_CA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
7634 vBIT(val, 2, 7)
7636 #define VXGE_HAL_RF_USDC_1_CA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
7637 vBIT(val, 0, 2)
7638 #define VXGE_HAL_RF_USDC_1_CA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
7639 vBIT(val, 2, 7)
7641 #define VXGE_HAL_RF_G3IF_FB_RD1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7642 vBIT(val, 0, 2)
7643 #define VXGE_HAL_RF_G3IF_FB_RD1_FBIF_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8)
7645 #define VXGE_HAL_RF_G3IF_FB_RD2_FBIF_NMB_IO_REPAIR_STATUS(val) vBIT(val, 0, 2)
7646 #define VXGE_HAL_RF_G3IF_FB_RD2_FBIF_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8)
7648 #define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7649 vBIT(val, 0, 2)
7650 #define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP1_FBIF_NMB_IO_ALL_FUSE(val)\
7651 vBIT(val, 2, 8)
7653 #define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\
7654 vBIT(val, 0, 2)
7655 #define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\
7656 vBIT(val, 2, 8)
7658 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
7659 vBIT(val, 0, 2)
7660 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK1_FUSE(val)\
7661 vBIT(val, 2, 8)
7662 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
7663 vBIT(val, 10, 2)
7664 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK0_FUSE(val)\
7665 vBIT(val, 12, 8)
7666 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
7667 vBIT(val, 20, 2)
7669 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7670 vBIT(val, 0, 2)
7671 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK1_FUSE(val)\
7672 vBIT(val, 2, 8)
7673 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
7674 vBIT(val, 10, 2)
7675 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK0_FUSE(val)\
7676 vBIT(val, 12, 8)
7677 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
7678 vBIT(val, 20, 2)
7680 #define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\
7681 vBIT(val, 0, 2)
7682 #define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK1_FUSE(val)\
7683 vBIT(val, 2, 8)
7684 #define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
7685 vBIT(val, 10, 2)
7686 #define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK0_FUSE(val)\
7687 vBIT(val, 12, 8)
7688 #define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
7689 vBIT(val, 20, 2)
7691 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7692 vBIT(val, 0, 2)
7693 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A1_FBIF_NMB_IO_ALL_FUSE(val)\
7694 vBIT(val, 2, 7)
7696 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A2_FBIF_NMB_IO_REPAIR_STATUS(val)\
7697 vBIT(val, 0, 2)
7698 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A2_FBIF_NMB_IO_ALL_FUSE(val)\
7699 vBIT(val, 2, 7)
7701 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A3_FBIF_NMB_IO_REPAIR_STATUS(val)\
7702 vBIT(val, 0, 2)
7703 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A3_FBIF_NMB_IO_ALL_FUSE(val)\
7704 vBIT(val, 2, 7)
7706 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7707 vBIT(val, 0, 2)
7708 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B1_FBIF_NMB_IO_ALL_FUSE(val)\
7709 vBIT(val, 2, 7)
7711 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B2_FBIF_NMB_IO_REPAIR_STATUS(val)\
7712 vBIT(val, 0, 2)
7713 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B2_FBIF_NMB_IO_ALL_FUSE(val)\
7714 vBIT(val, 2, 7)
7716 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B3_FBIF_NMB_IO_REPAIR_STATUS(val)\
7717 vBIT(val, 0, 2)
7718 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B3_FBIF_NMB_IO_ALL_FUSE(val)\
7719 vBIT(val, 2, 7)
7721 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_REPAIR_STATUS(val)\
7722 vBIT(val, 0, 2)
7723 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_FUSE(val)\
7724 vBIT(val, 2, 8)
7725 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
7726 vBIT(val, 10, 2)
7727 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_FUSE(val)\
7728 vBIT(val, 12, 8)
7729 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
7730 vBIT(val, 20, 2)
7732 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7733 vBIT(val, 0, 2)
7734 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_FUSE(val)\
7735 vBIT(val, 2, 8)
7736 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
7737 vBIT(val, 10, 2)
7738 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_FUSE(val)\
7739 vBIT(val, 12, 8)
7740 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
7741 vBIT(val, 20, 2)
7743 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_REPAIR_STATUS(val)\
7744 vBIT(val, 0, 2)
7745 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_FUSE(val)\
7746 vBIT(val, 2, 7)
7747 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
7748 vBIT(val, 9, 3)
7749 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_FUSE(val)\
7750 vBIT(val, 12, 7)
7751 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
7752 vBIT(val, 19, 3)
7754 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7755 vBIT(val, 0, 2)
7756 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_FUSE(val)\
7757 vBIT(val, 2, 7)
7758 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
7759 vBIT(val, 9, 3)
7760 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_FUSE(val)\
7761 vBIT(val, 12, 7)
7762 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
7763 vBIT(val, 19, 3)
7765 #define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_REPAIR_STATUS(val)\
7766 vBIT(val, 0, 2)
7767 #define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_FUSE(val)\
7768 vBIT(val, 2, 8)
7769 #define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
7770 vBIT(val, 10, 2)
7771 #define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_FUSE(val)\
7772 vBIT(val, 12, 8)
7773 #define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
7774 vBIT(val, 20, 2)
7776 #define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_REPAIR_STATUS(val)\
7777 vBIT(val, 0, 2)
7778 #define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_FUSE(val)\
7779 vBIT(val, 2, 7)
7780 #define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
7781 vBIT(val, 9, 3)
7782 #define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_FUSE(val)\
7783 vBIT(val, 12, 7)
7784 #define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
7785 vBIT(val, 19, 3)
7787 #define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
7788 vBIT(val, 0, 2)
7789 #define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_0_FBIF_NMB_IO_ALL_FUSE(val)\
7790 vBIT(val, 2, 7)
7792 #define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7793 vBIT(val, 0, 2)
7794 #define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_1_FBIF_NMB_IO_ALL_FUSE(val)\
7795 vBIT(val, 2, 7)
7797 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
7798 vBIT(val, 0, 2)
7799 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_0_FBIF_NMB_IO_ALL_FUSE(val)\
7800 vBIT(val, 2, 7)
7802 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
7803 vBIT(val, 0, 2)
7804 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_0_FBIF_NMB_IO_ALL_FUSE(val)\
7805 vBIT(val, 2, 7)
7807 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7808 vBIT(val, 0, 2)
7809 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_1_FBIF_NMB_IO_ALL_FUSE(val)\
7810 vBIT(val, 2, 7)
7812 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7813 vBIT(val, 0, 2)
7814 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_1_FBIF_NMB_IO_ALL_FUSE(val)\
7815 vBIT(val, 2, 7)
7817 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
7818 vBIT(val, 0, 2)
7819 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_0_FBIF_NMB_IO_ALL_FUSE(val)\
7820 vBIT(val, 2, 6)
7822 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
7823 vBIT(val, 0, 2)
7824 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_0_FBIF_NMB_IO_ALL_FUSE(val)\
7825 vBIT(val, 2, 6)
7827 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
7828 vBIT(val, 0, 2)
7829 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_0_FBIF_NMB_IO_ALL_FUSE(val)\
7830 vBIT(val, 2, 6)
7832 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7833 vBIT(val, 0, 2)
7834 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_1_FBIF_NMB_IO_ALL_FUSE(val)\
7835 vBIT(val, 2, 6)
7837 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7838 vBIT(val, 0, 2)
7839 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_1_FBIF_NMB_IO_ALL_FUSE(val)\
7840 vBIT(val, 2, 6)
7842 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
7843 vBIT(val, 0, 2)
7844 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_1_FBIF_NMB_IO_ALL_FUSE(val)\
7845 vBIT(val, 2, 6)
7847 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_2_FBIF_NMB_IO_REPAIR_STATUS(val)\
7848 vBIT(val, 0, 2)
7849 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_2_FBIF_NMB_IO_ALL_FUSE(val)\
7850 vBIT(val, 2, 6)
7852 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_2_FBIF_NMB_IO_REPAIR_STATUS(val)\
7853 vBIT(val, 0, 2)
7854 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_2_FBIF_NMB_IO_ALL_FUSE(val)\
7855 vBIT(val, 2, 6)
7857 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_2_FBIF_NMB_IO_REPAIR_STATUS(val)\
7858 vBIT(val, 0, 2)
7859 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_2_FBIF_NMB_IO_ALL_FUSE(val)\
7860 vBIT(val, 2, 6)
7862 #define VXGE_HAL_RF_TMAC_TPA2M_DA_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\
7863 vBIT(val, 0, 2)
7864 #define VXGE_HAL_RF_TMAC_TPA2M_DA_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\
7865 vBIT(val, 2, 6)
7867 #define VXGE_HAL_RF_TMAC_TPA2M_SB_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\
7868 vBIT(val, 0, 2)
7869 #define VXGE_HAL_RF_TMAC_TPA2M_SB_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\
7870 vBIT(val, 2, 8)
7872 #define VXGE_HAL_RF_XT_TRACE_RTL_TOP_MP_MSG_NMB_IO_REPAIR_STATUS(val)\
7873 vBIT(val, 0, 2)
7874 #define VXGE_HAL_RF_XT_TRACE_RTL_TOP_MP_MSG_NMB_IO_ALL_FUSE(val)\
7875 vBIT(val, 2, 8)
7877 #define VXGE_HAL_RF_MP_XT_DTAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
7878 vBIT(val, 0, 2)
7879 #define VXGE_HAL_RF_MP_XT_DTAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
7881 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
7882 vBIT(val, 0, 2)
7883 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
7884 vBIT(val, 2, 7)
7886 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
7887 vBIT(val, 0, 2)
7888 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
7889 vBIT(val, 2, 7)
7891 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
7892 vBIT(val, 0, 2)
7893 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
7894 vBIT(val, 2, 7)
7896 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
7897 vBIT(val, 0, 2)
7898 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
7899 vBIT(val, 2, 7)
7901 #define VXGE_HAL_RF_MP_XT_ITAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
7902 vBIT(val, 0, 2)
7903 #define VXGE_HAL_RF_MP_XT_ITAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
7905 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
7906 vBIT(val, 0, 2)
7907 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
7908 vBIT(val, 2, 7)
7910 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
7911 vBIT(val, 0, 2)
7912 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
7913 vBIT(val, 2, 7)
7915 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
7916 vBIT(val, 0, 2)
7917 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
7918 vBIT(val, 2, 7)
7920 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
7921 vBIT(val, 0, 2)
7922 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
7923 vBIT(val, 2, 7)
7925 #define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\
7926 vBIT(val, 0, 2)
7927 #define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val)\
7928 vBIT(val, 2, 8)
7930 #define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\
7931 vBIT(val, 0, 2)
7932 #define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val)\
7933 vBIT(val, 2, 8)
7935 #define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\
7936 vBIT(val, 0, 2)
7937 #define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 7)
7939 #define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\
7940 vBIT(val, 0, 2)
7941 #define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 7)
7943 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\
7944 vBIT(val, 0, 2)
7945 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
7947 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\
7948 vBIT(val, 0, 2)
7949 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
7951 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_2_MSG_NMB_IO_REPAIR_STATUS(val)\
7952 vBIT(val, 0, 2)
7953 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_2_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
7955 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\
7956 vBIT(val, 0, 2)
7957 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val)\
7958 vBIT(val, 2, 6)
7960 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\
7961 vBIT(val, 0, 2)
7962 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val)\
7963 vBIT(val, 2, 6)
7965 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_2_MSG_NMB_IO_REPAIR_STATUS(val)\
7966 vBIT(val, 0, 2)
7967 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_2_MSG_NMB_IO_ALL_FUSE(val)\
7968 vBIT(val, 2, 6)
7970 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
7971 vBIT(val, 0, 2)
7972 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
7973 vBIT(val, 2, 6)
7975 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
7976 vBIT(val, 0, 2)
7977 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
7978 vBIT(val, 2, 6)
7980 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
7981 vBIT(val, 0, 2)
7982 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
7983 vBIT(val, 2, 6)
7985 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
7986 vBIT(val, 0, 2)
7987 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
7988 vBIT(val, 2, 6)
7990 #define VXGE_HAL_RF_MSG_TXPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
7991 vBIT(val, 0, 2)
7992 #define VXGE_HAL_RF_MSG_TXPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\
7993 vBIT(val, 2, 7)
7995 #define VXGE_HAL_RF_MSG_RXPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
7996 vBIT(val, 0, 2)
7997 #define VXGE_HAL_RF_MSG_RXPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\
7998 vBIT(val, 2, 7)
8000 #define VXGE_HAL_RF_MSG_RPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
8001 vBIT(val, 0, 2)
8002 #define VXGE_HAL_RF_MSG_RPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\
8003 vBIT(val, 2, 7)
8005 #define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
8006 vBIT(val, 0, 2)
8007 #define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK1_FUSE(val) vBIT(val, 2, 8)
8008 #define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK1_ADD_FUSE(val)\
8009 vBIT(val, 10, 2)
8010 #define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK0_FUSE(val) vBIT(val, 12, 8)
8011 #define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK0_ADD_FUSE(val)\
8012 vBIT(val, 20, 2)
8014 #define VXGE_HAL_RF_TIM_VBLS_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
8015 vBIT(val, 0, 2)
8016 #define VXGE_HAL_RF_TIM_VBLS_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8)
8018 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
8019 vBIT(val, 0, 2)
8020 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
8021 vBIT(val, 2, 6)
8023 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
8024 vBIT(val, 0, 2)
8025 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
8026 vBIT(val, 2, 6)
8028 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_0_MSG_NMB_IO_REPAIR_STATUS(val)\
8029 vBIT(val, 0, 2)
8030 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_0_MSG_NMB_IO_ALL_FUSE(val)\
8031 vBIT(val, 2, 6)
8033 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
8034 vBIT(val, 0, 2)
8035 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
8036 vBIT(val, 2, 6)
8038 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
8039 vBIT(val, 0, 2)
8040 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
8041 vBIT(val, 2, 6)
8043 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_1_MSG_NMB_IO_REPAIR_STATUS(val)\
8044 vBIT(val, 0, 2)
8045 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_1_MSG_NMB_IO_ALL_FUSE(val)\
8046 vBIT(val, 2, 6)
8048 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_2_MSG_NMB_IO_REPAIR_STATUS(val)\
8049 vBIT(val, 0, 2)
8050 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_2_MSG_NMB_IO_ALL_FUSE(val)\
8051 vBIT(val, 2, 6)
8053 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_2_MSG_NMB_IO_REPAIR_STATUS(val)\
8054 vBIT(val, 0, 2)
8055 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_2_MSG_NMB_IO_ALL_FUSE(val)\
8056 vBIT(val, 2, 6)
8058 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_2_MSG_NMB_IO_REPAIR_STATUS(val)\
8059 vBIT(val, 0, 2)
8060 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_2_MSG_NMB_IO_ALL_FUSE(val)\
8061 vBIT(val, 2, 6)
8063 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_3_MSG_NMB_IO_REPAIR_STATUS(val)\
8064 vBIT(val, 0, 2)
8065 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_3_MSG_NMB_IO_ALL_FUSE(val)\
8066 vBIT(val, 2, 6)
8068 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_3_MSG_NMB_IO_REPAIR_STATUS(val)\
8069 vBIT(val, 0, 2)
8070 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_3_MSG_NMB_IO_ALL_FUSE(val)\
8071 vBIT(val, 2, 6)
8073 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_3_MSG_NMB_IO_REPAIR_STATUS(val)\
8074 vBIT(val, 0, 2)
8075 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_3_MSG_NMB_IO_ALL_FUSE(val)\
8076 vBIT(val, 2, 6)
8078 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_4_MSG_NMB_IO_REPAIR_STATUS(val)\
8079 vBIT(val, 0, 2)
8080 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_4_MSG_NMB_IO_ALL_FUSE(val)\
8081 vBIT(val, 2, 6)
8083 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_4_MSG_NMB_IO_REPAIR_STATUS(val)\
8084 vBIT(val, 0, 2)
8085 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_4_MSG_NMB_IO_ALL_FUSE(val)\
8086 vBIT(val, 2, 6)
8088 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_4_MSG_NMB_IO_REPAIR_STATUS(val)\
8089 vBIT(val, 0, 2)
8090 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_4_MSG_NMB_IO_ALL_FUSE(val)\
8091 vBIT(val, 2, 6)
8093 #define VXGE_HAL_RF_XT_TRACE_RTL_TOP_UP_MSG_NMB_IO_REPAIR_STATUS(val)\
8094 vBIT(val, 0, 2)
8095 #define VXGE_HAL_RF_XT_TRACE_RTL_TOP_UP_MSG_NMB_IO_ALL_FUSE(val)\
8096 vBIT(val, 2, 8)
8098 #define VXGE_HAL_RF_UP_XT_DTAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
8099 vBIT(val, 0, 2)
8100 #define VXGE_HAL_RF_UP_XT_DTAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
8102 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
8103 vBIT(val, 0, 2)
8104 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
8105 vBIT(val, 2, 7)
8107 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
8108 vBIT(val, 0, 2)
8109 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
8110 vBIT(val, 2, 7)
8112 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
8113 vBIT(val, 0, 2)
8114 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
8115 vBIT(val, 2, 7)
8117 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
8118 vBIT(val, 0, 2)
8119 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
8120 vBIT(val, 2, 7)
8122 #define VXGE_HAL_RF_UP_XT_ITAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
8123 vBIT(val, 0, 2)
8124 #define VXGE_HAL_RF_UP_XT_ITAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
8126 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
8127 vBIT(val, 0, 2)
8128 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
8129 vBIT(val, 2, 7)
8131 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
8132 vBIT(val, 0, 2)
8133 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
8134 vBIT(val, 2, 7)
8136 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
8137 vBIT(val, 0, 2)
8138 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
8139 vBIT(val, 2, 7)
8141 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
8142 vBIT(val, 0, 2)
8143 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
8144 vBIT(val, 2, 7)
8146 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
8147 vBIT(val, 0, 2)
8148 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\
8149 vBIT(val, 2, 7)
8150 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
8151 vBIT(val, 9, 4)
8152 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\
8153 vBIT(val, 13, 7)
8154 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
8155 vBIT(val, 20, 4)
8157 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
8158 vBIT(val, 0, 2)
8159 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\
8160 vBIT(val, 2, 7)
8161 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
8162 vBIT(val, 9, 4)
8163 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\
8164 vBIT(val, 13, 7)
8165 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
8166 vBIT(val, 20, 4)
8168 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
8169 vBIT(val, 0, 2)
8170 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\
8171 vBIT(val, 2, 7)
8172 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
8173 vBIT(val, 9, 3)
8174 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\
8175 vBIT(val, 12, 7)
8176 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
8177 vBIT(val, 19, 3)
8179 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
8180 vBIT(val, 0, 2)
8181 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\
8182 vBIT(val, 2, 7)
8183 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
8184 vBIT(val, 9, 3)
8185 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\
8186 vBIT(val, 12, 7)
8187 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
8188 vBIT(val, 19, 3)
8190 #define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
8191 vBIT(val, 0, 2)
8192 #define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\
8193 vBIT(val, 2, 7)
8195 #define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
8196 vBIT(val, 0, 2)
8197 #define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\
8198 vBIT(val, 2, 7)
8200 #define VXGE_HAL_RF_RXPE_XT0_FRM_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\
8201 vBIT(val, 0, 2)
8202 #define VXGE_HAL_RF_RXPE_XT0_FRM_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\
8203 vBIT(val, 2, 8)
8205 #define VXGE_HAL_RF_RPE_PDM_RCMD_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\
8206 vBIT(val, 0, 2)
8207 #define VXGE_HAL_RF_RPE_PDM_RCMD_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\
8208 vBIT(val, 2, 8)
8210 #define VXGE_HAL_RF_RPE_RCQ_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\
8211 vBIT(val, 0, 2)
8212 #define VXGE_HAL_RF_RPE_RCQ_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8)
8214 #define VXGE_HAL_RF_RPE_RCO_PBLE_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\
8215 vBIT(val, 0, 2)
8216 #define VXGE_HAL_RF_RPE_RCO_PBLE_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\
8217 vBIT(val, 2, 8)
8219 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
8220 vBIT(val, 0, 2)
8221 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\
8222 vBIT(val, 2, 7)
8223 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
8224 vBIT(val, 9, 4)
8225 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\
8226 vBIT(val, 13, 7)
8227 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
8228 vBIT(val, 20, 4)
8230 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
8231 vBIT(val, 0, 2)
8232 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\
8233 vBIT(val, 2, 7)
8234 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
8235 vBIT(val, 9, 4)
8236 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\
8237 vBIT(val, 13, 7)
8238 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
8239 vBIT(val, 20, 4)
8241 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
8242 vBIT(val, 0, 2)
8243 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\
8244 vBIT(val, 2, 8)
8245 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
8246 vBIT(val, 10, 2)
8247 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\
8248 vBIT(val, 12, 8)
8249 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
8250 vBIT(val, 20, 2)
8252 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
8253 vBIT(val, 0, 2)
8254 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\
8255 vBIT(val, 2, 8)
8256 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
8257 vBIT(val, 10, 2)
8258 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\
8259 vBIT(val, 12, 8)
8260 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
8261 vBIT(val, 20, 2)
8263 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
8264 vBIT(val, 0, 2)
8265 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\
8266 vBIT(val, 2, 7)
8267 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
8268 vBIT(val, 9, 3)
8269 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\
8270 vBIT(val, 12, 7)
8271 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
8272 vBIT(val, 19, 3)
8274 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
8275 vBIT(val, 0, 2)
8276 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\
8277 vBIT(val, 2, 7)
8278 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
8279 vBIT(val, 9, 3)
8280 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\
8281 vBIT(val, 12, 7)
8282 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
8283 vBIT(val, 19, 3)
8285 #define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
8286 vBIT(val, 0, 2)
8287 #define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\
8288 vBIT(val, 2, 8)
8290 #define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
8291 vBIT(val, 0, 2)
8292 #define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\
8293 vBIT(val, 2, 8)
8295 #define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
8296 vBIT(val, 0, 2)
8297 #define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\
8298 vBIT(val, 2, 8)
8300 #define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
8301 vBIT(val, 0, 2)
8302 #define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\
8303 vBIT(val, 2, 8)
8305 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\
8306 vBIT(val, 0, 2)
8307 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\
8308 vBIT(val, 2, 8)
8310 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\
8311 vBIT(val, 0, 2)
8312 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\
8313 vBIT(val, 2, 8)
8315 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\
8316 vBIT(val, 0, 2)
8317 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\
8318 vBIT(val, 2, 8)
8320 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\
8321 vBIT(val, 0, 2)
8322 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\
8323 vBIT(val, 2, 8)
8325 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\
8326 vBIT(val, 0, 2)
8327 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\
8328 vBIT(val, 2, 8)
8330 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_5_PCI_NMB_IO_REPAIR_STATUS(val)\
8331 vBIT(val, 0, 2)
8332 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_5_PCI_NMB_IO_ALL_FUSE(val)\
8333 vBIT(val, 2, 8)
8335 #define VXGE_HAL_RF_PCI_SOT_BUF_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\
8336 vBIT(val, 0, 2)
8337 #define VXGE_HAL_RF_PCI_SOT_BUF_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val)\
8338 vBIT(val, 2, 6)
8340 #define VXGE_HAL_RF_PCI_RX_PH_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\
8341 vBIT(val, 0, 2)
8342 #define VXGE_HAL_RF_PCI_RX_PH_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8)
8344 #define VXGE_HAL_RF_PCI_RX_NPH_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\
8345 vBIT(val, 0, 2)
8346 #define VXGE_HAL_RF_PCI_RX_NPH_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8)
8348 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\
8349 vBIT(val, 0, 2)
8350 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\
8351 vBIT(val, 2, 7)
8353 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\
8354 vBIT(val, 0, 2)
8355 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\
8356 vBIT(val, 2, 7)
8358 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\
8359 vBIT(val, 0, 2)
8360 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\
8361 vBIT(val, 2, 7)
8363 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\
8364 vBIT(val, 0, 2)
8365 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\
8366 vBIT(val, 2, 7)
8368 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\
8369 vBIT(val, 0, 2)
8370 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\
8371 vBIT(val, 2, 7)
8373 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_5_PCI_NMB_IO_REPAIR_STATUS(val)\
8374 vBIT(val, 0, 2)
8375 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_5_PCI_NMB_IO_ALL_FUSE(val)\
8376 vBIT(val, 2, 7)
8378 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_6_PCI_NMB_IO_REPAIR_STATUS(val)\
8379 vBIT(val, 0, 2)
8380 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_6_PCI_NMB_IO_ALL_FUSE(val)\
8381 vBIT(val, 2, 7)
8383 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_7_PCI_NMB_IO_REPAIR_STATUS(val)\
8384 vBIT(val, 0, 2)
8385 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_7_PCI_NMB_IO_ALL_FUSE(val)\
8386 vBIT(val, 2, 7)
8388 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_8_PCI_NMB_IO_REPAIR_STATUS(val)\
8389 vBIT(val, 0, 2)
8390 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_8_PCI_NMB_IO_ALL_FUSE(val)\
8391 vBIT(val, 2, 7)
8393 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_9_PCI_NMB_IO_REPAIR_STATUS(val)\
8394 vBIT(val, 0, 2)
8395 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_9_PCI_NMB_IO_ALL_FUSE(val)\
8396 vBIT(val, 2, 7)
8398 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_10_PCI_NMB_IO_REPAIR_STATUS(val)\
8399 vBIT(val, 0, 2)
8400 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_10_PCI_NMB_IO_ALL_FUSE(val)\
8401 vBIT(val, 2, 7)
8403 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_11_PCI_NMB_IO_REPAIR_STATUS(val)\
8404 vBIT(val, 0, 2)
8405 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_11_PCI_NMB_IO_ALL_FUSE(val)\
8406 vBIT(val, 2, 7)
8408 #define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\
8409 vBIT(val, 0, 2)
8410 #define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\
8411 vBIT(val, 2, 7)
8413 #define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\
8414 vBIT(val, 0, 2)
8415 #define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\
8416 vBIT(val, 2, 7)
8418 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\
8419 vBIT(val, 0, 2)
8420 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\
8421 vBIT(val, 2, 8)
8423 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\
8424 vBIT(val, 0, 2)
8425 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\
8426 vBIT(val, 2, 8)
8428 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\
8429 vBIT(val, 0, 2)
8430 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\
8431 vBIT(val, 2, 8)
8433 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\
8434 vBIT(val, 0, 2)
8435 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\
8436 vBIT(val, 2, 8)
8438 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\
8439 vBIT(val, 0, 2)
8440 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\
8441 vBIT(val, 2, 8)
8443 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC0_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8444 vBIT(val, 0, 2)
8445 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC0_RTDMA_NMB_IO_ALL_FUSE(val)\
8446 vBIT(val, 2, 8)
8448 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC1_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8449 vBIT(val, 0, 2)
8450 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC1_RTDMA_NMB_IO_ALL_FUSE(val)\
8451 vBIT(val, 2, 8)
8453 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC2_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8454 vBIT(val, 0, 2)
8455 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC2_RTDMA_NMB_IO_ALL_FUSE(val)\
8456 vBIT(val, 2, 8)
8458 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC3_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8459 vBIT(val, 0, 2)
8460 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC3_RTDMA_NMB_IO_ALL_FUSE(val)\
8461 vBIT(val, 2, 8)
8463 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC4_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8464 vBIT(val, 0, 2)
8465 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC4_RTDMA_NMB_IO_ALL_FUSE(val)\
8466 vBIT(val, 2, 8)
8468 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC5_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8469 vBIT(val, 0, 2)
8470 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC5_RTDMA_NMB_IO_ALL_FUSE(val)\
8471 vBIT(val, 2, 8)
8473 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC6_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8474 vBIT(val, 0, 2)
8475 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC6_RTDMA_NMB_IO_ALL_FUSE(val)\
8476 vBIT(val, 2, 8)
8478 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC7_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8479 vBIT(val, 0, 2)
8480 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC7_RTDMA_NMB_IO_ALL_FUSE(val)\
8481 vBIT(val, 2, 8)
8483 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8484 vBIT(val, 0, 2)
8485 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK1_FUSE(val)\
8486 vBIT(val, 2, 8)
8487 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
8488 vBIT(val, 10, 2)
8489 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK0_FUSE(val)\
8490 vBIT(val, 12, 8)
8491 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
8492 vBIT(val, 20, 2)
8494 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8495 vBIT(val, 0, 2)
8496 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK1_FUSE(val)\
8497 vBIT(val, 2, 8)
8498 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
8499 vBIT(val, 10, 2)
8500 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK0_FUSE(val)\
8501 vBIT(val, 12, 8)
8502 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
8503 vBIT(val, 20, 2)
8505 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8506 vBIT(val, 0, 2)
8507 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK1_FUSE(val)\
8508 vBIT(val, 2, 8)
8509 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
8510 vBIT(val, 10, 2)
8511 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK0_FUSE(val)\
8512 vBIT(val, 12, 8)
8513 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
8514 vBIT(val, 20, 2)
8516 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8517 vBIT(val, 0, 2)
8518 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK1_FUSE(val)\
8519 vBIT(val, 2, 8)
8520 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
8521 vBIT(val, 10, 2)
8522 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK0_FUSE(val)\
8523 vBIT(val, 12, 8)
8524 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
8525 vBIT(val, 20, 2)
8527 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8528 vBIT(val, 0, 2)
8529 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK1_FUSE(val)\
8530 vBIT(val, 2, 8)
8531 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
8532 vBIT(val, 10, 2)
8533 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK0_FUSE(val)\
8534 vBIT(val, 12, 8)
8535 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
8536 vBIT(val, 20, 2)
8538 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8539 vBIT(val, 0, 2)
8540 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK1_FUSE(val)\
8541 vBIT(val, 2, 8)
8542 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
8543 vBIT(val, 10, 2)
8544 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK0_FUSE(val)\
8545 vBIT(val, 12, 8)
8546 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
8547 vBIT(val, 20, 2)
8549 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8550 vBIT(val, 0, 2)
8551 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK1_FUSE(val)\
8552 vBIT(val, 2, 8)
8553 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
8554 vBIT(val, 10, 2)
8555 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK0_FUSE(val)\
8556 vBIT(val, 12, 8)
8557 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
8558 vBIT(val, 20, 2)
8560 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_REPAIR_STATUS(val)\
8561 vBIT(val, 0, 2)
8562 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK1_FUSE(val)\
8563 vBIT(val, 2, 8)
8564 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
8565 vBIT(val, 10, 2)
8566 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK0_FUSE(val)\
8567 vBIT(val, 12, 8)
8568 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
8569 vBIT(val, 20, 2)
8571 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8572 vBIT(val, 0, 2)
8573 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W0_WRDMA_NMB_IO_ALL_FUSE(val)\
8574 vBIT(val, 2, 8)
8576 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8577 vBIT(val, 0, 2)
8578 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W0_WRDMA_NMB_IO_ALL_FUSE(val)\
8579 vBIT(val, 2, 8)
8581 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8582 vBIT(val, 0, 2)
8583 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_WRAPPER0_WRDMA_NMB_IO_ALL_FUSE(val)\
8584 vBIT(val, 2, 8)
8586 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8587 vBIT(val, 0, 2)
8588 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W1_WRDMA_NMB_IO_ALL_FUSE(val)\
8589 vBIT(val, 2, 8)
8591 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8592 vBIT(val, 0, 2)
8593 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W1_WRDMA_NMB_IO_ALL_FUSE(val)\
8594 vBIT(val, 2, 8)
8596 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8597 vBIT(val, 0, 2)
8598 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W1_WRDMA_NMB_IO_ALL_FUSE(val)\
8599 vBIT(val, 2, 8)
8601 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8602 vBIT(val, 0, 2)
8603 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_WRAPPER2_WRDMA_NMB_IO_ALL_FUSE(val)\
8604 vBIT(val, 2, 8)
8606 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8607 vBIT(val, 0, 2)
8608 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W2_WRDMA_NMB_IO_ALL_FUSE(val)\
8609 vBIT(val, 2, 8)
8611 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8612 vBIT(val, 0, 2)
8613 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W2_WRDMA_NMB_IO_ALL_FUSE(val)\
8614 vBIT(val, 2, 8)
8616 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8617 vBIT(val, 0, 2)
8618 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK1_FUSE(val)\
8619 vBIT(val, 2, 8)
8620 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK1_ADD_FUSE(val)\
8621 vBIT(val, 10, 2)
8622 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK0_FUSE(val)\
8623 vBIT(val, 12, 8)
8624 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK0_ADD_FUSE(val)\
8625 vBIT(val, 20, 2)
8627 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8628 vBIT(val, 0, 2)
8629 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK1_FUSE(val)\
8630 vBIT(val, 2, 8)
8631 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK1_ADD_FUSE(val)\
8632 vBIT(val, 10, 2)
8633 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK0_FUSE(val)\
8634 vBIT(val, 12, 8)
8635 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK0_ADD_FUSE(val)\
8636 vBIT(val, 20, 2)
8638 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8639 vBIT(val, 0, 2)
8640 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_0_WRDMA_NMB_IO_ALL_FUSE(val)\
8641 vBIT(val, 2, 8)
8643 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8644 vBIT(val, 0, 2)
8645 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_1_WRDMA_NMB_IO_ALL_FUSE(val)\
8646 vBIT(val, 2, 8)
8648 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_2_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8649 vBIT(val, 0, 2)
8650 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_2_WRDMA_NMB_IO_ALL_FUSE(val)\
8651 vBIT(val, 2, 8)
8653 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_3_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8654 vBIT(val, 0, 2)
8655 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_3_WRDMA_NMB_IO_ALL_FUSE(val)\
8656 vBIT(val, 2, 8)
8658 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_4_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8659 vBIT(val, 0, 2)
8660 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_4_WRDMA_NMB_IO_ALL_FUSE(val)\
8661 vBIT(val, 2, 8)
8663 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_5_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8664 vBIT(val, 0, 2)
8665 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_5_WRDMA_NMB_IO_ALL_FUSE(val)\
8666 vBIT(val, 2, 8)
8668 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_6_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8669 vBIT(val, 0, 2)
8670 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_6_WRDMA_NMB_IO_ALL_FUSE(val)\
8671 vBIT(val, 2, 8)
8673 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_7_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8674 vBIT(val, 0, 2)
8675 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_7_WRDMA_NMB_IO_ALL_FUSE(val)\
8676 vBIT(val, 2, 8)
8678 #define VXGE_HAL_RF_ROCRC_IMMDBUF_RTL_TOP_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8679 vBIT(val, 0, 2)
8680 #define VXGE_HAL_RF_ROCRC_IMMDBUF_RTL_TOP_WRDMA_NMB_IO_ALL_FUSE(val)\
8681 vBIT(val, 2, 8)
8683 #define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8684 vBIT(val, 0, 2)
8685 #define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_0_WRDMA_NMB_IO_ALL_FUSE(val)\
8686 vBIT(val, 2, 8)
8688 #define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
8689 vBIT(val, 0, 2)
8690 #define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_1_WRDMA_NMB_IO_ALL_FUSE(val)\
8691 vBIT(val, 2, 8)
8693 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8694 vBIT(val, 0, 2)
8695 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK1_FUSE(val)\
8696 vBIT(val, 2, 6)
8697 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\
8698 vBIT(val, 8, 2)
8699 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK0_FUSE(val)\
8700 vBIT(val, 10, 6)
8701 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\
8702 vBIT(val, 16, 2)
8704 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8705 vBIT(val, 0, 2)
8706 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK1_FUSE(val)\
8707 vBIT(val, 2, 6)
8708 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\
8709 vBIT(val, 8, 2)
8710 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK0_FUSE(val)\
8711 vBIT(val, 10, 6)
8712 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\
8713 vBIT(val, 16, 2)
8715 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8716 vBIT(val, 0, 2)
8717 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK1_FUSE(val)\
8718 vBIT(val, 2, 6)
8719 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\
8720 vBIT(val, 8, 2)
8721 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK0_FUSE(val)\
8722 vBIT(val, 10, 6)
8723 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\
8724 vBIT(val, 16, 2)
8726 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8727 vBIT(val, 0, 2)
8728 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK1_FUSE(val)\
8729 vBIT(val, 2, 6)
8730 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\
8731 vBIT(val, 8, 2)
8732 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK0_FUSE(val)\
8733 vBIT(val, 10, 6)
8734 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\
8735 vBIT(val, 16, 2)
8737 #define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8738 vBIT(val, 0, 2)
8739 #define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK1_FUSE(val)\
8740 vBIT(val, 2, 7)
8741 #define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\
8742 vBIT(val, 9, 2)
8743 #define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK0_FUSE(val)\
8744 vBIT(val, 11, 7)
8745 #define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\
8746 vBIT(val, 18, 2)
8748 #define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8749 vBIT(val, 0, 2)
8750 #define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\
8751 vBIT(val, 2, 7)
8753 #define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8754 vBIT(val, 0, 2)
8755 #define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\
8756 vBIT(val, 2, 7)
8758 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8759 vBIT(val, 0, 2)
8760 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_0_XGMAC_NMB_IO_ALL_FUSE(val)\
8761 vBIT(val, 2, 8)
8763 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8764 vBIT(val, 0, 2)
8765 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_0_XGMAC_NMB_IO_ALL_FUSE(val)\
8766 vBIT(val, 2, 8)
8768 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8769 vBIT(val, 0, 2)
8770 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_1_XGMAC_NMB_IO_ALL_FUSE(val)\
8771 vBIT(val, 2, 8)
8773 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8774 vBIT(val, 0, 2)
8775 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_1_XGMAC_NMB_IO_ALL_FUSE(val)\
8776 vBIT(val, 2, 8)
8778 #define VXGE_HAL_RF_RMAC_DS_LKP_RTL_TOP_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8779 vBIT(val, 0, 2)
8780 #define VXGE_HAL_RF_RMAC_DS_LKP_RTL_TOP_XGMAC_NMB_IO_ALL_FUSE(val)\
8781 vBIT(val, 2, 6)
8783 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC0_XGMAC_NMB_IO_REP_STATUS(val)\
8784 vBIT(val, 0, 2)
8785 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC0_XGMAC_NMB_IO_ALL_FUSE(val)\
8786 vBIT(val, 2, 8)
8788 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC0_XGMAC_NMB_IO_REP_STATUS(val)\
8789 vBIT(val, 0, 2)
8790 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC0_XGMAC_NMB_IO_ALL_FUSE(val)\
8791 vBIT(val, 2, 8)
8793 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC1_XGMAC_NMB_IO_REP_STATUS(val)\
8794 vBIT(val, 0, 2)
8795 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC1_XGMAC_NMB_IO_ALL_FUSE(val)\
8796 vBIT(val, 2, 8)
8798 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC1_XGMAC_NMB_IO_REP_STATUS(val)\
8799 vBIT(val, 0, 2)
8800 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC1_XGMAC_NMB_IO_ALL_FUSE(val)\
8801 vBIT(val, 2, 8)
8803 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC2_XGMAC_NMB_IO_REP_STATUS(val)\
8804 vBIT(val, 0, 2)
8805 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC2_XGMAC_NMB_IO_ALL_FUSE(val)\
8806 vBIT(val, 2, 8)
8808 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC2_XGMAC_NMB_IO_REP_STATUS(val)\
8809 vBIT(val, 0, 2)
8810 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC2_XGMAC_NMB_IO_ALL_FUSE(val)\
8811 vBIT(val, 2, 8)
8813 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8814 vBIT(val, 0, 2)
8815 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\
8816 vBIT(val, 2, 8)
8818 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8819 vBIT(val, 0, 2)
8820 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\
8821 vBIT(val, 2, 8)
8823 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8824 vBIT(val, 0, 2)
8825 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_2_XGMAC_NMB_IO_ALL_FUSE(val)\
8826 vBIT(val, 2, 8)
8828 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8829 vBIT(val, 0, 2)
8830 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_3_XGMAC_NMB_IO_ALL_FUSE(val)\
8831 vBIT(val, 2, 8)
8833 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8834 vBIT(val, 0, 2)
8835 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\
8836 vBIT(val, 2, 6)
8838 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8839 vBIT(val, 0, 2)
8840 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\
8841 vBIT(val, 2, 6)
8843 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8844 vBIT(val, 0, 2)
8845 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_2_XGMAC_NMB_IO_ALL_FUSE(val)\
8846 vBIT(val, 2, 6)
8848 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8849 vBIT(val, 0, 2)
8850 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_3_XGMAC_NMB_IO_ALL_FUSE(val)\
8851 vBIT(val, 2, 6)
8853 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_4_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8854 vBIT(val, 0, 2)
8855 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_4_XGMAC_NMB_IO_ALL_FUSE(val)\
8856 vBIT(val, 2, 6)
8858 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_5_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8859 vBIT(val, 0, 2)
8860 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_5_XGMAC_NMB_IO_ALL_FUSE(val)\
8861 vBIT(val, 2, 6)
8863 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_6_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8864 vBIT(val, 0, 2)
8865 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_6_XGMAC_NMB_IO_ALL_FUSE(val)\
8866 vBIT(val, 2, 6)
8868 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_7_XGMAC_NMB_IO_REPAIR_STATUS(val)\
8869 vBIT(val, 0, 2)
8870 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_7_XGMAC_NMB_IO_ALL_FUSE(val)\
8871 vBIT(val, 2, 6)
8873 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_0_XGMAC_NMB_IO_REP_STATUS(val)\
8874 vBIT(val, 0, 2)
8875 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_0_XGMAC_NMB_IO_ALL_FUSE(val)\
8876 vBIT(val, 2, 7)
8878 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_0_XGMAC_NMB_IO_REP_STATUS(val)\
8879 vBIT(val, 0, 2)
8880 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_0_XGMAC_NMB_IO_ALL_FUSE(val)\
8881 vBIT(val, 2, 7)
8883 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_1_XGMAC_NMB_IO_REP_STATUS(val)\
8884 vBIT(val, 0, 2)
8885 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_1_XGMAC_NMB_IO_ALL_FUSE(val)\
8886 vBIT(val, 2, 7)
8888 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_1_XGMAC_NMB_IO_REP_STATUS(val)\
8889 vBIT(val, 0, 2)
8890 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_1_XGMAC_NMB_IO_ALL_FUSE(val)\
8891 vBIT(val, 2, 7)
8893 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_2_XGMAC_NMB_IO_REP_STATUS(val)\
8894 vBIT(val, 0, 2)
8895 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_2_XGMAC_NMB_IO_ALL_FUSE(val)\
8896 vBIT(val, 2, 7)
8898 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_2_XGMAC_NMB_IO_REP_STATUS(val)\
8899 vBIT(val, 0, 2)
8900 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_2_XGMAC_NMB_IO_ALL_FUSE(val)\
8901 vBIT(val, 2, 7)
8903 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_3_XGMAC_NMB_IO_REP_STATUS(val)\
8904 vBIT(val, 0, 2)
8905 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_3_XGMAC_NMB_IO_ALL_FUSE(val)\
8906 vBIT(val, 2, 7)
8908 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_3_XGMAC_NMB_IO_REP_STATUS(val)\
8909 vBIT(val, 0, 2)
8910 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_3_XGMAC_NMB_IO_ALL_FUSE(val)\
8911 vBIT(val, 2, 7)
8913 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_4_XGMAC_NMB_IO_REP_STATUS(val)\
8914 vBIT(val, 0, 2)
8915 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_4_XGMAC_NMB_IO_ALL_FUSE(val)\
8916 vBIT(val, 2, 7)
8918 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_4_XGMAC_NMB_IO_REP_STATUS(val)\
8919 vBIT(val, 0, 2)
8920 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_4_XGMAC_NMB_IO_ALL_FUSE(val)\
8921 vBIT(val, 2, 7)
8930 #define VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) vBIT(val, 24, 8)
8935 #define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_0_SA_CAL(val) vBIT(val, 0, 8)
8936 #define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_0_SB_CAL(val) vBIT(val, 8, 8)
8938 #define VXGE_HAL_G3IFCMD_FB_DLL_CK0_CMD_ADD_DLL_0_S(val) vBIT(val, 25, 7)
8940 #define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_UPD(val) vBIT(val, 44, 4)
8943 #define VXGE_HAL_G3IFCMD_FB_IO_CTRL_TERM(val) vBIT(val, 13, 3)
8945 #define VXGE_HAL_G3IFCMD_FB_IOCAL_RST_CYCLES(val) vBIT(val, 0, 16)
8946 #define VXGE_HAL_G3IFCMD_FB_IOCAL_RST_VALUE(val) vBIT(val, 17, 7)
8947 #define VXGE_HAL_G3IFCMD_FB_IOCAL_CORR_VALUE(val) vBIT(val, 24, 8)
8948 #define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE0(val) vBIT(val, 33, 7)
8949 #define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE1(val) vBIT(val, 41, 7)
8950 #define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE2(val) vBIT(val, 49, 7)
8951 #define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE3(val) vBIT(val, 57, 7)
8953 #define VXGE_HAL_G3IFCMD_FB_MASTER_DLL_CK_DDR_GR_RAW(val) vBIT(val, 1, 7)
8954 #define VXGE_HAL_G3IFCMD_FB_MASTER_DLL_CK_SAMPLE(val) vBIT(val, 8, 8)
8958 #define VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_START_CODE(val) vBIT(val, 9, 7)
8959 #define VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_END_CODE(val) vBIT(val, 17, 7)
8963 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
8964 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
8965 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
8966 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
8967 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
8972 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
8974 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
8975 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
8976 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
8980 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
8983 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\
8984 vBIT(val, 4, 4)
8985 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\
8986 vBIT(val, 9, 7)
8987 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\
8988 vBIT(val, 17, 7)
8989 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
8990 vBIT(val, 36, 4)
8991 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\
8992 vBIT(val, 41, 7)
8993 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\
8994 vBIT(val, 49, 7)
8996 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
8997 vBIT(val, 0, 32)
8998 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
8999 vBIT(val, 32, 16)
9000 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
9001 vBIT(val, 48, 16)
9003 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\
9004 vBIT(val, 0, 16)
9005 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\
9006 vBIT(val, 16, 16)
9008 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\
9009 vBIT(val, 1, 7)
9010 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\
9011 vBIT(val, 9, 7)
9013 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\
9014 vBIT(val, 28, 4)
9027 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\
9028 vBIT(val, 6, 2)
9029 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\
9030 vBIT(val, 8, 8)
9032 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
9033 vBIT(val, 1, 7)
9034 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
9035 vBIT(val, 9, 7)
9036 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\
9037 vBIT(val, 16, 24)
9038 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\
9039 vBIT(val, 40, 24)
9041 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
9042 vBIT(val, 1, 7)
9043 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
9044 vBIT(val, 9, 7)
9045 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\
9046 vBIT(val, 16, 24)
9047 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\
9048 vBIT(val, 40, 24)
9050 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
9051 vBIT(val, 9, 7)
9052 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
9053 vBIT(val, 25, 7)
9054 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
9055 vBIT(val, 41, 7)
9056 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
9057 vBIT(val, 57, 7)
9059 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_TIMER_VALUE(val)\
9060 vBIT(val, 0, 16)
9063 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_SA_CAL(val)\
9064 vBIT(val, 0, 8)
9065 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_SB_CAL(val)\
9066 vBIT(val, 8, 8)
9067 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_ATRA_SA_CAL(val)\
9068 vBIT(val, 32, 8)
9069 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_ATRA_SB_CAL(val)\
9070 vBIT(val, 40, 8)
9071 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_DDR_DLL_S(val)\
9072 vBIT(val, 57, 7)
9077 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9079 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
9080 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
9081 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9085 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9088 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\
9089 vBIT(val, 4, 4)
9090 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\
9091 vBIT(val, 9, 7)
9092 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\
9093 vBIT(val, 17, 7)
9094 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
9095 vBIT(val, 36, 4)
9096 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\
9097 vBIT(val, 41, 7)
9098 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\
9099 vBIT(val, 49, 7)
9101 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
9102 vBIT(val, 0, 32)
9103 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
9104 vBIT(val, 32, 16)
9105 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
9106 vBIT(val, 48, 16)
9108 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\
9109 vBIT(val, 0, 16)
9110 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\
9111 vBIT(val, 16, 16)
9113 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\
9114 vBIT(val, 1, 7)
9115 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\
9116 vBIT(val, 9, 7)
9118 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_TCNT(val) vBIT(val, 28, 4)
9131 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\
9132 vBIT(val, 6, 2)
9133 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\
9134 vBIT(val, 8, 8)
9136 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
9137 vBIT(val, 1, 7)
9138 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
9139 vBIT(val, 9, 7)
9140 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\
9141 vBIT(val, 16, 24)
9142 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\
9143 vBIT(val, 40, 24)
9145 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
9146 vBIT(val, 1, 7)
9147 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
9148 vBIT(val, 9, 7)
9149 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\
9150 vBIT(val, 16, 24)
9151 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\
9152 vBIT(val, 40, 24)
9154 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
9155 vBIT(val, 9, 7)
9156 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
9157 vBIT(val, 25, 7)
9158 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
9159 vBIT(val, 41, 7)
9160 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
9161 vBIT(val, 57, 7)
9163 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
9168 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
9169 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
9170 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
9171 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
9172 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9177 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9179 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
9180 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
9181 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9185 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9188 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\
9189 vBIT(val, 4, 4)
9190 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\
9191 vBIT(val, 9, 7)
9192 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\
9193 vBIT(val, 17, 7)
9194 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
9195 vBIT(val, 36, 4)
9196 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\
9197 vBIT(val, 41, 7)
9198 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\
9199 vBIT(val, 49, 7)
9201 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
9202 vBIT(val, 0, 32)
9203 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
9204 vBIT(val, 32, 16)
9205 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
9206 vBIT(val, 48, 16)
9208 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\
9209 vBIT(val, 0, 16)
9210 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\
9211 vBIT(val, 16, 16)
9213 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\
9214 vBIT(val, 1, 7)
9215 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\
9216 vBIT(val, 9, 7)
9218 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_TCNT(val)\
9219 vBIT(val, 28, 4)
9232 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\
9233 vBIT(val, 6, 2)
9234 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\
9235 vBIT(val, 8, 8)
9237 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
9238 vBIT(val, 1, 7)
9239 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
9240 vBIT(val, 9, 7)
9241 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\
9242 vBIT(val, 16, 24)
9243 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\
9244 vBIT(val, 40, 24)
9246 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
9247 vBIT(val, 1, 7)
9248 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
9249 vBIT(val, 9, 7)
9250 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\
9251 vBIT(val, 16, 24)
9252 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\
9253 vBIT(val, 40, 24)
9255 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
9256 vBIT(val, 9, 7)
9257 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
9258 vBIT(val, 25, 7)
9259 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
9260 vBIT(val, 41, 7)
9261 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
9262 vBIT(val, 57, 7)
9264 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
9267 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
9268 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
9269 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
9270 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
9271 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9276 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9278 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
9279 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
9280 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9284 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9287 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\
9288 vBIT(val, 4, 4)
9289 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\
9290 vBIT(val, 9, 7)
9291 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\
9292 vBIT(val, 17, 7)
9293 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
9294 vBIT(val, 36, 4)
9295 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\
9296 vBIT(val, 41, 7)
9297 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\
9298 vBIT(val, 49, 7)
9300 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
9301 vBIT(val, 0, 32)
9302 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
9303 vBIT(val, 32, 16)
9304 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
9305 vBIT(val, 48, 16)
9307 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\
9308 vBIT(val, 0, 16)
9309 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\
9310 vBIT(val, 16, 16)
9312 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\
9313 vBIT(val, 1, 7)
9314 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\
9315 vBIT(val, 9, 7)
9317 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_TCNT(val) vBIT(val, 28, 4)
9330 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\
9331 vBIT(val, 6, 2)
9332 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\
9333 vBIT(val, 8, 8)
9335 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
9336 vBIT(val, 1, 7)
9337 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
9338 vBIT(val, 9, 7)
9339 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\
9340 vBIT(val, 16, 24)
9341 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\
9342 vBIT(val, 40, 24)
9344 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
9345 vBIT(val, 1, 7)
9346 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
9347 vBIT(val, 9, 7)
9348 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\
9349 vBIT(val, 16, 24)
9350 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\
9351 vBIT(val, 40, 24)
9353 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
9354 vBIT(val, 9, 7)
9355 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
9356 vBIT(val, 25, 7)
9357 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
9358 vBIT(val, 41, 7)
9359 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
9360 vBIT(val, 57, 7)
9362 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
9372 #define VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) vBIT(val, 24, 8)
9377 #define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_0_SA_CAL(val) vBIT(val, 0, 8)
9378 #define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_0_SB_CAL(val) vBIT(val, 8, 8)
9380 #define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_CMD_ADD_DLL_0_S(val) vBIT(val, 25, 7)
9382 #define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_UPD(val) vBIT(val, 44, 4)
9385 #define VXGE_HAL_G3IFCMD_CMU_IO_CTRL_TERM(val) vBIT(val, 13, 3)
9387 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_RST_CYCLES(val) vBIT(val, 0, 16)
9388 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_RST_VALUE(val) vBIT(val, 17, 7)
9389 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_CORR_VALUE(val) vBIT(val, 24, 8)
9390 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE0(val) vBIT(val, 33, 7)
9391 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE1(val) vBIT(val, 41, 7)
9392 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE2(val) vBIT(val, 49, 7)
9393 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE3(val) vBIT(val, 57, 7)
9395 #define VXGE_HAL_G3IFCMD_CMU_MASTER_DLL_CK_DDR_GR_RAW(val) vBIT(val, 1, 7)
9396 #define VXGE_HAL_G3IFCMD_CMU_MASTER_DLL_CK_SAMPLE(val) vBIT(val, 8, 8)
9400 #define VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_START_CODE(val) vBIT(val, 9, 7)
9401 #define VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_END_CODE(val) vBIT(val, 17, 7)
9405 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
9406 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
9407 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
9408 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
9409 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9414 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9416 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
9417 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
9418 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9422 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9426 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\
9427 vBIT(val, 4, 4)
9428 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\
9429 vBIT(val, 9, 7)
9430 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\
9431 vBIT(val, 17, 7)
9432 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
9433 vBIT(val, 36, 4)
9434 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\
9435 vBIT(val, 41, 7)
9436 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\
9437 vBIT(val, 49, 7)
9439 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
9440 vBIT(val, 0, 32)
9441 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
9442 vBIT(val, 32, 16)
9443 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
9444 vBIT(val, 48, 16)
9446 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\
9447 vBIT(val, 0, 16)
9448 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\
9449 vBIT(val, 16, 16)
9451 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\
9452 vBIT(val, 1, 7)
9453 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\
9454 vBIT(val, 9, 7)
9456 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\
9457 vBIT(val, 28, 4)
9470 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\
9471 vBIT(val, 6, 2)
9472 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\
9473 vBIT(val, 8, 8)
9475 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
9476 vBIT(val, 1, 7)
9477 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
9478 vBIT(val, 9, 7)
9479 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\
9480 vBIT(val, 16, 24)
9481 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\
9482 vBIT(val, 40, 24)
9484 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
9485 vBIT(val, 1, 7)
9486 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
9487 vBIT(val, 9, 7)
9488 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\
9489 vBIT(val, 16, 24)
9490 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\
9491 vBIT(val, 40, 24)
9493 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
9494 vBIT(val, 9, 7)
9495 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
9496 vBIT(val, 25, 7)
9497 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
9498 vBIT(val, 41, 7)
9499 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
9500 vBIT(val, 57, 7)
9502 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
9505 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
9506 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
9507 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
9508 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
9509 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9514 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9516 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
9517 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
9518 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9522 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9525 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\
9526 vBIT(val, 4, 4)
9527 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\
9528 vBIT(val, 9, 7)
9529 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\
9530 vBIT(val, 17, 7)
9531 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
9532 vBIT(val, 36, 4)
9533 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\
9534 vBIT(val, 41, 7)
9535 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\
9536 vBIT(val, 49, 7)
9538 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
9539 vBIT(val, 0, 32)
9540 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
9541 vBIT(val, 32, 16)
9542 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
9543 vBIT(val, 48, 16)
9545 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\
9546 vBIT(val, 0, 16)
9547 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\
9548 vBIT(val, 16, 16)
9550 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\
9551 vBIT(val, 1, 7)
9552 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\
9553 vBIT(val, 9, 7)
9555 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_TCNT(val)\
9556 vBIT(val, 28, 4)
9569 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\
9570 vBIT(val, 6, 2)
9571 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\
9572 vBIT(val, 8, 8)
9574 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
9575 vBIT(val, 1, 7)
9576 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
9577 vBIT(val, 9, 7)
9578 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\
9579 vBIT(val, 16, 24)
9580 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\
9581 vBIT(val, 40, 24)
9583 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
9584 vBIT(val, 1, 7)
9585 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
9586 vBIT(val, 9, 7)
9587 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\
9588 vBIT(val, 16, 24)
9589 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\
9590 vBIT(val, 40, 24)
9592 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
9593 vBIT(val, 9, 7)
9594 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
9595 vBIT(val, 25, 7)
9596 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
9597 vBIT(val, 41, 7)
9598 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
9599 vBIT(val, 57, 7)
9601 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
9606 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
9607 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
9608 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
9609 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
9610 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9615 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9617 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
9618 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
9619 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9624 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_DLL_UPD(val)\
9625 vBIT(val, 21, 3)
9629 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\
9630 vBIT(val, 4, 4)
9631 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\
9632 vBIT(val, 9, 7)
9633 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\
9634 vBIT(val, 17, 7)
9635 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
9636 vBIT(val, 36, 4)
9637 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\
9638 vBIT(val, 41, 7)
9639 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\
9640 vBIT(val, 49, 7)
9642 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
9643 vBIT(val, 0, 32)
9644 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
9645 vBIT(val, 32, 16)
9646 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
9647 vBIT(val, 48, 16)
9649 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\
9650 vBIT(val, 0, 16)
9651 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\
9652 vBIT(val, 16, 16)
9654 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\
9655 vBIT(val, 1, 7)
9656 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\
9657 vBIT(val, 9, 7)
9659 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_TCNT(val)\
9660 vBIT(val, 28, 4)
9673 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\
9674 vBIT(val, 6, 2)
9675 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\
9676 vBIT(val, 8, 8)
9678 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
9679 vBIT(val, 1, 7)
9680 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
9681 vBIT(val, 9, 7)
9682 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\
9683 vBIT(val, 16, 24)
9684 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\
9685 vBIT(val, 40, 24)
9687 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
9688 vBIT(val, 1, 7)
9689 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
9690 vBIT(val, 9, 7)
9691 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\
9692 vBIT(val, 16, 24)
9693 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\
9694 vBIT(val, 40, 24)
9696 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
9697 vBIT(val, 9, 7)
9698 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
9699 vBIT(val, 25, 7)
9700 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
9701 vBIT(val, 41, 7)
9702 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
9703 vBIT(val, 57, 7)
9705 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
9708 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
9709 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
9710 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
9711 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
9712 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9717 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9719 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
9720 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
9721 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9725 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9728 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\
9729 vBIT(val, 4, 4)
9730 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\
9731 vBIT(val, 9, 7)
9732 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\
9733 vBIT(val, 17, 7)
9734 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
9735 vBIT(val, 36, 4)
9736 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\
9737 vBIT(val, 41, 7)
9738 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\
9739 vBIT(val, 49, 7)
9741 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
9742 vBIT(val, 0, 32)
9743 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
9744 vBIT(val, 32, 16)
9745 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
9746 vBIT(val, 48, 16)
9748 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\
9749 vBIT(val, 0, 16)
9750 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\
9751 vBIT(val, 16, 16)
9753 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\
9754 vBIT(val, 1, 7)
9755 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\
9756 vBIT(val, 9, 7)
9759 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_TCNT(val)\
9760 vBIT(val, 28, 4)
9773 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\
9774 vBIT(val, 6, 2)
9775 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\
9776 vBIT(val, 8, 8)
9778 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
9779 vBIT(val, 1, 7)
9780 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
9781 vBIT(val, 9, 7)
9782 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\
9783 vBIT(val, 16, 24)
9784 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\
9785 vBIT(val, 40, 24)
9787 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
9788 vBIT(val, 1, 7)
9789 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
9790 vBIT(val, 9, 7)
9791 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\
9792 vBIT(val, 16, 24)
9793 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\
9794 vBIT(val, 40, 24)
9796 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
9797 vBIT(val, 9, 7)
9798 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
9799 vBIT(val, 25, 7)
9800 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
9801 vBIT(val, 41, 7)
9802 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
9803 vBIT(val, 57, 7)
9805 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
9815 #define VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK(val)\
9816 vBIT(val, 24, 8)
9821 #define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_0_SA_CAL(val) vBIT(val, 0, 8)
9822 #define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_0_SB_CAL(val) vBIT(val, 8, 8)
9824 #define VXGE_HAL_G3IFCMD_CML_DLL_CK0_CMD_ADD_DLL_0_S(val) vBIT(val, 25, 7)
9826 #define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_UPD(val) vBIT(val, 44, 4)
9829 #define VXGE_HAL_G3IFCMD_CML_IO_CTRL_TERM(val) vBIT(val, 13, 3)
9831 #define VXGE_HAL_G3IFCMD_CML_IOCAL_RST_CYCLES(val) vBIT(val, 0, 16)
9832 #define VXGE_HAL_G3IFCMD_CML_IOCAL_RST_VALUE(val) vBIT(val, 17, 7)
9833 #define VXGE_HAL_G3IFCMD_CML_IOCAL_CORR_VALUE(val) vBIT(val, 24, 8)
9834 #define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE0(val)\
9835 vBIT(val, 33, 7)
9836 #define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE1(val)\
9837 vBIT(val, 41, 7)
9838 #define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE2(val)\
9839 vBIT(val, 49, 7)
9840 #define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE3(val)\
9841 vBIT(val, 57, 7)
9843 #define VXGE_HAL_G3IFCMD_CML_MASTER_DLL_CK_DDR_GR_RAW(val) vBIT(val, 1, 7)
9844 #define VXGE_HAL_G3IFCMD_CML_MASTER_DLL_CK_SAMPLE(val) vBIT(val, 8, 8)
9848 #define VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_START_CODE(val) vBIT(val, 9, 7)
9849 #define VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_END_CODE(val) vBIT(val, 17, 7)
9853 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
9854 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
9855 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_ATRA_SA_CAL(val)\
9856 vBIT(val, 32, 8)
9857 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_ATRA_SB_CAL(val)\
9858 vBIT(val, 40, 8)
9859 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9864 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9866 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
9867 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
9868 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9872 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9876 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\
9877 vBIT(val, 4, 4)
9878 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\
9879 vBIT(val, 9, 7)
9880 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\
9881 vBIT(val, 17, 7)
9882 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
9883 vBIT(val, 36, 4)
9884 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\
9885 vBIT(val, 41, 7)
9886 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\
9887 vBIT(val, 49, 7)
9889 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
9890 vBIT(val, 0, 32)
9891 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
9892 vBIT(val, 32, 16)
9893 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
9894 vBIT(val, 48, 16)
9896 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\
9897 vBIT(val, 0, 16)
9898 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\
9899 vBIT(val, 16, 16)
9901 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\
9902 vBIT(val, 1, 7)
9903 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\
9904 vBIT(val, 9, 7)
9906 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\
9907 vBIT(val, 28, 4)
9920 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\
9921 vBIT(val, 6, 2)
9922 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\
9923 vBIT(val, 8, 8)
9925 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
9926 vBIT(val, 1, 7)
9927 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
9928 vBIT(val, 9, 7)
9929 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\
9930 vBIT(val, 16, 24)
9931 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\
9932 vBIT(val, 40, 24)
9934 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
9935 vBIT(val, 1, 7)
9936 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
9937 vBIT(val, 9, 7)
9938 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\
9939 vBIT(val, 16, 24)
9940 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\
9941 vBIT(val, 40, 24)
9943 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
9944 vBIT(val, 9, 7)
9945 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
9946 vBIT(val, 25, 7)
9947 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
9948 vBIT(val, 41, 7)
9949 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
9950 vBIT(val, 57, 7)
9952 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
9955 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
9956 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
9957 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
9958 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
9959 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9964 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9966 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
9967 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
9968 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
9972 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
9975 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\
9976 vBIT(val, 4, 4)
9977 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\
9978 vBIT(val, 9, 7)
9979 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\
9980 vBIT(val, 17, 7)
9981 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
9982 vBIT(val, 36, 4)
9983 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\
9984 vBIT(val, 41, 7)
9985 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\
9986 vBIT(val, 49, 7)
9988 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
9989 vBIT(val, 0, 32)
9990 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
9991 vBIT(val, 32, 16)
9992 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
9993 vBIT(val, 48, 16)
9995 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\
9996 vBIT(val, 0, 16)
9997 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\
9998 vBIT(val, 16, 16)
10000 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\
10001 vBIT(val, 1, 7)
10002 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\
10003 vBIT(val, 9, 7)
10005 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_TCNT(val)\
10006 vBIT(val, 28, 4)
10019 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\
10020 vBIT(val, 6, 2)
10021 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\
10022 vBIT(val, 8, 8)
10024 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
10025 vBIT(val, 1, 7)
10026 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
10027 vBIT(val, 9, 7)
10028 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\
10029 vBIT(val, 16, 24)
10030 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\
10031 vBIT(val, 40, 24)
10033 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
10034 vBIT(val, 1, 7)
10035 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
10036 vBIT(val, 9, 7)
10037 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\
10038 vBIT(val, 16, 24)
10039 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\
10040 vBIT(val, 40, 24)
10042 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
10043 vBIT(val, 9, 7)
10044 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
10045 vBIT(val, 25, 7)
10046 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
10047 vBIT(val, 41, 7)
10048 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
10049 vBIT(val, 57, 7)
10051 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_TIMER_VALUE(val)\
10052 vBIT(val, 0, 16)
10057 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
10058 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
10059 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
10060 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
10061 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
10066 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
10068 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
10069 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
10070 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
10074 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
10078 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\
10079 vBIT(val, 4, 4)
10080 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\
10081 vBIT(val, 9, 7)
10082 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\
10083 vBIT(val, 17, 7)
10084 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
10085 vBIT(val, 36, 4)
10086 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\
10087 vBIT(val, 41, 7)
10088 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\
10089 vBIT(val, 49, 7)
10091 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
10092 vBIT(val, 0, 32)
10093 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
10094 vBIT(val, 32, 16)
10095 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
10096 vBIT(val, 48, 16)
10098 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\
10099 vBIT(val, 0, 16)
10100 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\
10101 vBIT(val, 16, 16)
10103 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\
10104 vBIT(val, 1, 7)
10105 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\
10106 vBIT(val, 9, 7)
10108 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_TCNT(val) \
10109 vBIT(val, 28, 4)
10122 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\
10123 vBIT(val, 6, 2)
10124 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\
10125 vBIT(val, 8, 8)
10127 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
10128 vBIT(val, 1, 7)
10129 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
10130 vBIT(val, 9, 7)
10131 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\
10132 vBIT(val, 16, 24)
10133 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\
10134 vBIT(val, 40, 24)
10136 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
10137 vBIT(val, 1, 7)
10138 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
10139 vBIT(val, 9, 7)
10140 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\
10141 vBIT(val, 16, 24)
10142 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\
10143 vBIT(val, 40, 24)
10145 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
10146 vBIT(val, 9, 7)
10147 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
10148 vBIT(val, 25, 7)
10149 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
10150 vBIT(val, 41, 7)
10151 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
10152 vBIT(val, 57, 7)
10154 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
10157 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8)
10158 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8)
10159 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
10160 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
10161 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
10166 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
10168 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8)
10169 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8)
10170 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
10174 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
10177 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\
10178 vBIT(val, 4, 4)
10179 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\
10180 vBIT(val, 9, 7)
10181 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\
10182 vBIT(val, 17, 7)
10183 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
10184 vBIT(val, 36, 4)
10185 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\
10186 vBIT(val, 41, 7)
10187 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\
10188 vBIT(val, 49, 7)
10190 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
10191 vBIT(val, 0, 32)
10192 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
10193 vBIT(val, 32, 16)
10194 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
10195 vBIT(val, 48, 16)
10197 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\
10198 vBIT(val, 0, 16)
10199 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\
10200 vBIT(val, 16, 16)
10202 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\
10203 vBIT(val, 1, 7)
10204 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\
10205 vBIT(val, 9, 7)
10207 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_TCNT(val)\
10208 vBIT(val, 28, 4)
10221 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\
10222 vBIT(val, 6, 2)
10223 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\
10224 vBIT(val, 8, 8)
10226 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
10227 vBIT(val, 1, 7)
10228 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
10229 vBIT(val, 9, 7)
10230 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\
10231 vBIT(val, 16, 24)
10232 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\
10233 vBIT(val, 40, 24)
10235 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
10236 vBIT(val, 1, 7)
10237 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
10238 vBIT(val, 9, 7)
10239 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\
10240 vBIT(val, 16, 24)
10241 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\
10242 vBIT(val, 40, 24)
10244 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
10245 vBIT(val, 9, 7)
10246 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
10247 vBIT(val, 25, 7)
10248 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
10249 vBIT(val, 41, 7)
10250 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
10251 vBIT(val, 57, 7)
10253 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
10258 #define VXGE_HAL_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) vBIT(val, 3, 5)
10262 #define VXGE_HAL_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val) vBIT(val, 16, 4)
10263 #define VXGE_HAL_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val) vBIT(val, 20, 4)
10265 #define VXGE_HAL_XGXS_CFG_PORT_SEL_INFO_1(val) vBIT(val, 29, 3)
10266 #define VXGE_HAL_XGXS_CFG_PORT_TX_LANE0_SKEW(val) vBIT(val, 32, 4)
10267 #define VXGE_HAL_XGXS_CFG_PORT_TX_LANE1_SKEW(val) vBIT(val, 36, 4)
10268 #define VXGE_HAL_XGXS_CFG_PORT_TX_LANE2_SKEW(val) vBIT(val, 40, 4)
10269 #define VXGE_HAL_XGXS_CFG_PORT_TX_LANE3_SKEW(val) vBIT(val, 44, 4)
10271 #define VXGE_HAL_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val) vBIT(val, 0, 4)
10272 #define VXGE_HAL_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) vBIT(val, 16, 48)
10274 #define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val)\
10275 vBIT(val, 0, 16)
10276 #define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val)\
10277 vBIT(val, 16, 16)
10278 #define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val)\
10279 vBIT(val, 32, 16)
10280 #define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val)\
10281 vBIT(val, 48, 16)
10283 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vBIT(val, 0, 4)
10284 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vBIT(val, 4, 4)
10286 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) vBIT(val, 12, 4)
10287 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val) vBIT(val, 16, 4)
10289 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val) vBIT(val, 24, 8)
10290 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) vBIT(val, 32, 4)
10291 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) vBIT(val, 36, 4)
10293 #define VXGE_HAL_XGXS_PMA_RESET_PORT_SERDES_RESET(val) vBIT(val, 0, 8)
10301 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE0(val) vBIT(val, 1, 3)
10302 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE1(val) vBIT(val, 5, 3)
10303 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE2(val) vBIT(val, 9, 3)
10304 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE3(val) vBIT(val, 13, 3)
10319 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_CKO_WORD_CON(val) vBIT(val, 37, 3)
10328 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE0(val) vBIT(val, 0, 4)
10329 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE1(val) vBIT(val, 4, 4)
10330 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE2(val) vBIT(val, 8, 4)
10331 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE3(val) vBIT(val, 12, 4)
10332 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE0(val) vBIT(val, 17, 3)
10333 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE1(val) vBIT(val, 21, 3)
10334 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE2(val) vBIT(val, 25, 3)
10335 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE3(val) vBIT(val, 29, 3)
10348 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE0(val) vBIT(val, 44, 2)
10349 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE1(val) vBIT(val, 46, 2)
10350 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE2(val) vBIT(val, 48, 2)
10351 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE3(val) vBIT(val, 50, 2)
10352 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_LVL(val) vBIT(val, 55, 5)
10358 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE0(val) vBIT(val, 5, 3)
10359 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE1(val) vBIT(val, 9, 3)
10360 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE2(val) vBIT(val, 13, 3)
10361 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE3(val) vBIT(val, 17, 3)
10362 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE0(val)\
10363 vBIT(val, 21, 3)
10364 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE1(val)\
10365 vBIT(val, 25, 3)
10366 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE2(val)\
10367 vBIT(val, 29, 3)
10368 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE3(val)\
10369 vBIT(val, 33, 3)
10375 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE0(val) vBIT(val, 4, 2)
10376 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE1(val) vBIT(val, 6, 2)
10377 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE2(val) vBIT(val, 8, 2)
10378 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE3(val) vBIT(val, 10, 2)
10381 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_LVL(val) vBIT(val, 19, 5)
10382 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_CKO_ALIVE_CON(val) vBIT(val, 28, 2)
10384 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_INT_CTL(val) vBIT(val, 33, 3)
10385 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_PROP_CTL(val) vBIT(val, 37, 3)
10387 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE0(val)\
10388 vBIT(val, 0, 2)
10389 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE1(val)\
10390 vBIT(val, 2, 2)
10391 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE2(val)\
10392 vBIT(val, 4, 2)
10393 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE3(val)\
10394 vBIT(val, 6, 2)
10422 #define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_ADDR(val) vBIT(val, 16, 16)
10423 #define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_DATA(val) vBIT(val, 48, 16)
10427 #define VXGE_HAL_XGXS_INFO_PORT_XMACJ_INFO_0(val) vBIT(val, 0, 32)
10428 #define VXGE_HAL_XGXS_INFO_PORT_XMACJ_INFO_1(val) vBIT(val, 32, 32)
10430 #define VXGE_HAL_RATEMGMT_CFG_PORT_MODE(val) vBIT(val, 2, 2)
10447 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val)\
10448 vBIT(val, 16, 4)
10449 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESP(val)\
10450 vBIT(val, 20, 4)
10451 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESP(val)\
10452 vBIT(val, 24, 4)
10459 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4(val) vBIT(val, 16, 4)
10460 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX(val) vBIT(val, 20, 4)
10461 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vBIT(val, 24, 4)
10465 #define VXGE_HAL_ANBE_CFG_PORT_RESET_CFG_REGS(val) vBIT(val, 0, 8)
10466 #define VXGE_HAL_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE(val) vBIT(val, 10, 2)
10467 #define VXGE_HAL_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE(val) vBIT(val, 14, 2)
10471 #define VXGE_HAL_ANBE_MGR_CTRL_PORT_ADDR(val) vBIT(val, 15, 9)
10472 #define VXGE_HAL_ANBE_MGR_CTRL_PORT_DATA(val) vBIT(val, 32, 32)
10487 #define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val)\
10488 vBIT(val, 18, 6)
10505 #define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val)\
10506 vBIT(val, 56, 4)
10507 #define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val)\
10508 vBIT(val, 60, 4)
10515 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val)\
10516 vBIT(val, 43, 5)
10522 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val)\
10523 vBIT(val, 54, 5)
10524 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val)\
10525 vBIT(val, 59, 5)
10527 #define VXGE_HAL_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32(val)\
10528 vBIT(val, 16, 16)
10529 #define VXGE_HAL_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0(val)\
10530 vBIT(val, 32, 32)
10537 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val)\
10538 vBIT(val, 10, 6)
10559 #define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val)\
10560 vBIT(val, 4, 7)
10561 #define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val)\
10562 vBIT(val, 11, 5)
10569 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val)\
10570 vBIT(val, 5, 11)
10571 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1(val)\
10572 vBIT(val, 16, 16)
10573 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2(val)\
10574 vBIT(val, 32, 16)
10577 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE(val) vBIT(val, 5, 3)
10578 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD(val) vBIT(val, 11, 5)
10579 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR(val) vBIT(val, 16, 16)
10580 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DATA(val) vBIT(val, 32, 16)
10581 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ST_PATTERN(val) vBIT(val, 49, 2)
10583 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_PRTAD(val) vBIT(val, 55, 5)
10592 #define VXGE_HAL_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val) vBIT(val, 0, 17)
10596 #define VXGE_HAL_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val) vBIT(val, 0, 8)
10597 #define VXGE_HAL_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val) vBIT(val, 8, 8)
10598 #define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_0(val) vBIT(val, 16, 8)
10599 #define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_1(val) vBIT(val, 24, 8)
10600 #define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_2(val) vBIT(val, 32, 8)
10601 #define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_3(val) vBIT(val, 40, 8)
10605 #define VXGE_HAL_FAU_ADAPTIVE_LRO_VPATH_ENABLE_EN(val) vBIT(val, 0, 17)
10607 #define VXGE_HAL_FAU_ADAPTIVE_LRO_BASE_SID_VP_VALUE(val) vBIT(val, 2, 6)
10608 #define VXGE_HAL_FAU_ADAPTIVE_LRO_BASE_SID_VP_USE_HASH_WIDTH(val)\
10609 vBIT(val, 11, 5)