Lines Matching refs:CSR_SETBIT_1
249 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
250 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
256 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
374 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
410 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
441 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
454 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
469 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
479 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
496 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
499 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
508 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
2059 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES);
2063 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
2065 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
2070 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
2073 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
2234 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2239 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2241 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2880 CSR_SETBIT_1(sc, VGE_DIAGCTL,