dev/ral/rt2661.c

243 		error = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
325 		rt2661_free_tx_ring(sc, &sc->txq[ac]);
343 	rt2661_free_tx_ring(sc, &sc->txq[0]);
344 	rt2661_free_tx_ring(sc, &sc->txq[1]);
345 	rt2661_free_tx_ring(sc, &sc->txq[2]);
346 	rt2661_free_tx_ring(sc, &sc->txq[3]);
852 	struct rt2661_tx_ring *txq;
868 		txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq;
871 		data = &txq->data[txq->stat];
915 		DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat);
917 		txq->queued--;
918 		if (++txq->stat >= txq->count)	/* faster than % count */
919 			txq->stat = 0;
930 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq)
935 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD);
938 		desc = &txq->desc[txq->next];
939 		data = &txq->data[txq->next];
945 		bus_dmamap_sync(txq->data_dmat, data->map,
947 		bus_dmamap_unload(txq->data_dmat, data->map);
952 		DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next);
954 		if (++txq->next >= txq->count)	/* faster than % count */
955 			txq->next = 0;
958 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1158 		rt2661_tx_dma_intr(sc, &sc->txq[0]);
1161 		rt2661_tx_dma_intr(sc, &sc->txq[1]);
1164 		rt2661_tx_dma_intr(sc, &sc->txq[2]);
1167 		rt2661_tx_dma_intr(sc, &sc->txq[3]);
1364 	struct rt2661_tx_ring *txq = &sc->txq[ac];
1400 	data = &txq->data[txq->cur];
1401 	desc = &txq->desc[txq->cur];
1403 	error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs,
1420 	bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1421 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1423 	txq->queued++;
1424 	txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1435 	struct rt2661_tx_ring *txq = &sc->txq[ac];
1497 	data = &txq->data[txq->cur];
1498 	desc = &txq->desc[txq->cur];
1500 	error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs,
1518 		error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0,
1562 	bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1563 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1566 	    m0->m_pkthdr.len, txq->cur, rate);
1569 	txq->queued++;
1570 	txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1613 		if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) {
2265 	RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2266 	RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2267 	RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2268 	RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2422 		rt2661_reset_tx_ring(sc, &sc->txq[0]);
2423 		rt2661_reset_tx_ring(sc, &sc->txq[1]);
2424 		rt2661_reset_tx_ring(sc, &sc->txq[2]);
2425 		rt2661_reset_tx_ring(sc, &sc->txq[3]);