Lines Matching refs:hw
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
55 * @hw: pointer to the hardware structure
60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
64 status = ixgbe_clock_out_i2c_byte(hw, byte);
67 return ixgbe_get_i2c_ack(hw);
72 * @hw: pointer to the hardware structure
77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
81 status = ixgbe_clock_in_i2c_byte(hw, byte);
85 return ixgbe_clock_out_i2c_bit(hw, FALSE);
105 * @hw: pointer to the hardware structure
113 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
116 u32 swfw_mask = hw->phy.phy_semaphore_mask;
129 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 ixgbe_i2c_start(hw);
133 if (ixgbe_out_i2c_byte_ack(hw, addr))
136 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
139 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
142 if (ixgbe_out_i2c_byte_ack(hw, csum))
145 ixgbe_i2c_start(hw);
147 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
150 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
153 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
156 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
159 if (ixgbe_clock_out_i2c_bit(hw, FALSE))
161 ixgbe_i2c_stop(hw);
163 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
168 ixgbe_i2c_bus_clear(hw);
170 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
183 * @hw: pointer to the hardware structure
191 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
194 u32 swfw_mask = hw->phy.phy_semaphore_mask;
206 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
208 ixgbe_i2c_start(hw);
210 if (ixgbe_out_i2c_byte_ack(hw, addr))
213 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
216 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
219 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
222 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
225 if (ixgbe_out_i2c_byte_ack(hw, csum))
227 ixgbe_i2c_stop(hw);
229 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
233 ixgbe_i2c_bus_clear(hw);
235 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
248 * @hw: pointer to the hardware structure
252 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
254 struct ixgbe_phy_info *phy = &hw->phy;
286 * @hw: pointer to hardware structure
291 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
295 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
301 if (ixgbe_get_phy_id(hw))
304 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
306 if (hw->phy.type == ixgbe_phy_unknown) {
307 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
312 hw->phy.type = ixgbe_phy_cu_unknown;
314 hw->phy.type = ixgbe_phy_generic;
322 * @hw: pointer to hardware structure
326 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
333 if (!hw->phy.phy_semaphore_mask) {
334 if (hw->bus.lan_id)
335 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
337 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
340 if (hw->phy.type != ixgbe_phy_unknown)
343 if (hw->phy.nw_mng_if_sel) {
344 phy_addr = (hw->phy.nw_mng_if_sel &
347 if (ixgbe_probe_phy(hw, phy_addr))
354 if (ixgbe_probe_phy(hw, phy_addr)) {
365 hw->phy.addr = 0;
372 * @hw: pointer to the hardware structure
379 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
386 if (hw->mac.type == ixgbe_mac_82598EB)
389 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
401 * @hw: pointer to hardware structure
404 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
411 hw->phy.addr = phy_addr;
412 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
425 * @hw: pointer to hardware structure
428 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
436 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
441 hw->phy.id = (u32)(phy_id_high << 16);
442 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
445 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
446 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
497 * @hw: pointer to hardware structure
499 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
507 if (hw->phy.type == ixgbe_phy_unknown)
508 status = ixgbe_identify_phy_generic(hw);
510 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
514 if (!hw->phy.reset_if_overtemp &&
515 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
519 if (ixgbe_check_reset_blocked(hw))
526 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
537 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
538 status = hw->phy.ops.read_reg(hw,
550 status = hw->phy.ops.read_reg(hw,
577 * @hw: pointer to hardware structure
581 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
589 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
592 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
602 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
620 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
623 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
633 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
648 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
658 * @hw: pointer to hardware structure
662 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
666 u32 gssr = hw->phy.phy_semaphore_mask;
670 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
673 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
675 hw->mac.ops.release_swfw_sync(hw, gssr);
683 * @hw: pointer to hardware structure
688 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
694 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
699 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
702 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
712 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
728 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
731 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
741 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
757 * @hw: pointer to hardware structure
762 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
766 u32 gssr = hw->phy.phy_semaphore_mask;
770 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
771 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
773 hw->mac.ops.release_swfw_sync(hw, gssr);
783 * @hw: pointer to hardware structure
787 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
796 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
799 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
804 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
808 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
812 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
816 if (hw->mac.type == ixgbe_mac_X550) {
819 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
825 if ((hw->phy.autoneg_advertised &
833 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
837 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
842 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
848 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
852 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
857 if (ixgbe_check_reset_blocked(hw))
861 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
866 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
874 * @hw: pointer to hardware structure
877 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
889 hw->phy.autoneg_advertised = 0;
892 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
895 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
898 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
901 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
904 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
907 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
910 ixgbe_setup_phy_link(hw);
917 * @hw: pointer to hardware structure
922 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
927 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
934 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
936 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
938 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
940 switch (hw->mac.type) {
942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
943 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
947 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
958 * @hw: pointer to hardware structure
962 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
971 if (!hw->phy.speeds_supported)
972 status = ixgbe_get_copper_speeds_supported(hw);
974 *speed = hw->phy.speeds_supported;
980 * @hw: pointer to hardware structure
985 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1008 status = hw->phy.ops.read_reg(hw,
1029 * @hw: pointer to hardware structure
1033 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1042 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1046 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1051 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1054 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1061 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1066 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1069 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1076 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1081 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1084 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1090 if (ixgbe_check_reset_blocked(hw))
1094 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1099 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1107 * @hw: pointer to hardware structure
1110 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1117 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1126 * @hw: pointer to hardware structure
1129 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1136 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1145 * @hw: pointer to hardware structure
1147 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1159 if (ixgbe_check_reset_blocked(hw))
1162 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1166 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1171 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1185 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1190 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1196 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1211 ret_val = hw->eeprom.ops.read(hw, data_offset,
1217 ret_val = hw->eeprom.ops.read(hw, data_offset,
1221 hw->phy.ops.write_reg(hw, phy_offset,
1261 * @hw: pointer to hardware structure
1265 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1271 switch (hw->mac.ops.get_media_type(hw)) {
1273 status = ixgbe_identify_sfp_module_generic(hw);
1277 status = ixgbe_identify_qsfp_module_generic(hw);
1281 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1291 * @hw: pointer to hardware structure
1295 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1299 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1310 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1311 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1317 hw->mac.ops.set_lan_id(hw);
1319 status = hw->phy.ops.read_i2c_eeprom(hw,
1327 hw->phy.type = ixgbe_phy_sfp_unsupported;
1330 status = hw->phy.ops.read_i2c_eeprom(hw,
1337 status = hw->phy.ops.read_i2c_eeprom(hw,
1343 status = hw->phy.ops.read_i2c_eeprom(hw,
1366 if (hw->mac.type == ixgbe_mac_82598EB) {
1368 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1370 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1372 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1374 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1377 if (hw->bus.lan_id == 0)
1378 hw->phy.sfp_type =
1381 hw->phy.sfp_type =
1384 hw->phy.ops.read_i2c_eeprom(
1385 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1389 if (hw->bus.lan_id == 0)
1390 hw->phy.sfp_type =
1393 hw->phy.sfp_type =
1396 hw->phy.sfp_type =
1402 if (hw->bus.lan_id == 0)
1403 hw->phy.sfp_type =
1406 hw->phy.sfp_type =
1409 if (hw->bus.lan_id == 0)
1410 hw->phy.sfp_type =
1413 hw->phy.sfp_type =
1416 if (hw->bus.lan_id == 0)
1417 hw->phy.sfp_type =
1420 hw->phy.sfp_type =
1423 if (hw->bus.lan_id == 0)
1424 hw->phy.sfp_type =
1427 hw->phy.sfp_type =
1430 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1434 if (hw->phy.sfp_type != stored_sfp_type)
1435 hw->phy.sfp_setup_needed = TRUE;
1438 hw->phy.multispeed_fiber = FALSE;
1443 hw->phy.multispeed_fiber = TRUE;
1446 if (hw->phy.type != ixgbe_phy_nl) {
1447 hw->phy.id = identifier;
1448 status = hw->phy.ops.read_i2c_eeprom(hw,
1455 status = hw->phy.ops.read_i2c_eeprom(hw,
1462 status = hw->phy.ops.read_i2c_eeprom(hw,
1477 hw->phy.type =
1482 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1484 hw->phy.type = ixgbe_phy_sfp_ftl;
1487 hw->phy.type = ixgbe_phy_sfp_avago;
1490 hw->phy.type = ixgbe_phy_sfp_intel;
1494 hw->phy.type =
1497 hw->phy.type =
1500 hw->phy.type = ixgbe_phy_sfp_unknown;
1514 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1517 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1518 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1519 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1520 hw->phy.type = ixgbe_phy_sfp_unsupported;
1526 if (hw->mac.type == ixgbe_mac_82598EB) {
1531 ixgbe_get_device_caps(hw, &enforce_sfp);
1533 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1536 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1537 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1538 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1540 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1543 if (hw->allow_unsupported_sfp == TRUE) {
1544 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1548 hw->phy.type =
1562 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1563 if (hw->phy.type != ixgbe_phy_nl) {
1564 hw->phy.id = 0;
1565 hw->phy.type = ixgbe_phy_unknown;
1572 * @hw: pointer to hardware structure
1576 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1584 hw->phy.ops.identify_sfp(hw);
1585 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1588 switch (hw->phy.type) {
1603 hw->phy.ops.read_i2c_eeprom(hw,
1605 hw->phy.ops.read_i2c_eeprom(hw,
1618 hw->phy.ops.read_i2c_eeprom(hw,
1634 * @hw: pointer to hardware structure
1638 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1642 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1655 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1656 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1662 hw->mac.ops.set_lan_id(hw);
1664 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1671 hw->phy.type = ixgbe_phy_sfp_unsupported;
1676 hw->phy.id = identifier;
1678 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1684 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1691 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1692 if (hw->bus.lan_id == 0)
1693 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1695 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1698 if (hw->bus.lan_id == 0)
1699 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1701 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1709 hw->phy.ops.read_i2c_eeprom(hw,
1713 hw->phy.ops.read_i2c_eeprom(hw,
1717 hw->phy.ops.read_i2c_eeprom(hw,
1730 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1731 if (hw->bus.lan_id == 0)
1732 hw->phy.sfp_type =
1735 hw->phy.sfp_type =
1739 hw->phy.type = ixgbe_phy_sfp_unsupported;
1745 if (hw->phy.sfp_type != stored_sfp_type)
1746 hw->phy.sfp_setup_needed = TRUE;
1749 hw->phy.multispeed_fiber = FALSE;
1754 hw->phy.multispeed_fiber = TRUE;
1759 status = hw->phy.ops.read_i2c_eeprom(hw,
1766 status = hw->phy.ops.read_i2c_eeprom(hw,
1773 status = hw->phy.ops.read_i2c_eeprom(hw,
1786 hw->phy.type = ixgbe_phy_qsfp_intel;
1788 hw->phy.type = ixgbe_phy_qsfp_unknown;
1790 ixgbe_get_device_caps(hw, &enforce_sfp);
1793 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1796 if (hw->allow_unsupported_sfp == TRUE) {
1797 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1801 hw->phy.type =
1815 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1816 hw->phy.id = 0;
1817 hw->phy.type = ixgbe_phy_unknown;
1824 * @hw: pointer to hardware structure
1831 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1836 u16 sfp_type = hw->phy.sfp_type;
1840 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1843 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1846 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1847 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1866 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1883 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1889 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1899 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1919 * @hw: pointer to hardware structure
1925 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1930 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1937 * @hw: pointer to hardware structure
1943 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1946 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1953 * @hw: pointer to hardware structure
1959 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1964 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1971 * @hw: pointer to hardware structure
1975 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1979 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1986 * @hw: pointer to hardware structure
1994 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2000 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2006 if (hw->mac.type >= ixgbe_mac_X550)
2008 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2012 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2015 ixgbe_i2c_start(hw);
2018 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2022 status = ixgbe_get_i2c_ack(hw);
2026 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2030 status = ixgbe_get_i2c_ack(hw);
2034 ixgbe_i2c_start(hw);
2037 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2041 status = ixgbe_get_i2c_ack(hw);
2045 status = ixgbe_clock_in_i2c_byte(hw, data);
2049 status = ixgbe_clock_out_i2c_bit(hw, nack);
2053 ixgbe_i2c_stop(hw);
2055 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2059 ixgbe_i2c_bus_clear(hw);
2061 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2077 * @hw: pointer to hardware structure
2084 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2087 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2093 * @hw: pointer to hardware structure
2100 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2103 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2109 * @hw: pointer to hardware structure
2117 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2123 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2127 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2132 ixgbe_i2c_start(hw);
2134 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2138 status = ixgbe_get_i2c_ack(hw);
2142 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2146 status = ixgbe_get_i2c_ack(hw);
2150 status = ixgbe_clock_out_i2c_byte(hw, data);
2154 status = ixgbe_get_i2c_ack(hw);
2158 ixgbe_i2c_stop(hw);
2160 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2164 ixgbe_i2c_bus_clear(hw);
2173 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2180 * @hw: pointer to hardware structure
2187 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2190 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2196 * @hw: pointer to hardware structure
2203 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2206 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2212 * @hw: pointer to hardware structure
2217 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2219 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2223 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2226 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2227 ixgbe_raise_i2c_clk(hw, &i2cctl);
2232 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2237 ixgbe_lower_i2c_clk(hw, &i2cctl);
2246 * @hw: pointer to hardware structure
2252 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2254 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2255 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2256 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2257 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2262 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2263 ixgbe_raise_i2c_clk(hw, &i2cctl);
2268 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2276 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2277 IXGBE_WRITE_FLUSH(hw);
2283 * @hw: pointer to hardware structure
2288 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2297 ixgbe_clock_in_i2c_bit(hw, &bit);
2306 * @hw: pointer to hardware structure
2311 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2322 status = ixgbe_clock_out_i2c_bit(hw, bit);
2329 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2330 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2331 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2332 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2333 IXGBE_WRITE_FLUSH(hw);
2340 * @hw: pointer to hardware structure
2344 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2346 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2349 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2356 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2358 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2359 IXGBE_WRITE_FLUSH(hw);
2361 ixgbe_raise_i2c_clk(hw, &i2cctl);
2369 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2370 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2382 ixgbe_lower_i2c_clk(hw, &i2cctl);
2392 * @hw: pointer to hardware structure
2397 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2399 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2400 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2405 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2407 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2408 IXGBE_WRITE_FLUSH(hw);
2410 ixgbe_raise_i2c_clk(hw, &i2cctl);
2415 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2416 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2418 ixgbe_lower_i2c_clk(hw, &i2cctl);
2428 * @hw: pointer to hardware structure
2433 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2436 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2440 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2442 ixgbe_raise_i2c_clk(hw, &i2cctl);
2447 ixgbe_lower_i2c_clk(hw, &i2cctl);
2464 * @hw: pointer to hardware structure
2470 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2472 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2481 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2485 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2487 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2488 IXGBE_WRITE_FLUSH(hw);
2492 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2493 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2500 * @hw: pointer to hardware structure
2506 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2510 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2511 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2513 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2514 IXGBE_WRITE_FLUSH(hw);
2522 * @hw: pointer to hardware structure
2529 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2531 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2537 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2539 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2542 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2543 IXGBE_WRITE_FLUSH(hw);
2552 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2553 IXGBE_WRITE_FLUSH(hw);
2557 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2558 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2570 * @hw: pointer to hardware structure
2576 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2578 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2585 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2586 IXGBE_WRITE_FLUSH(hw);
2590 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2600 * @hw: pointer to hardware structure
2605 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2612 ixgbe_i2c_start(hw);
2613 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2615 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2618 ixgbe_raise_i2c_clk(hw, &i2cctl);
2623 ixgbe_lower_i2c_clk(hw, &i2cctl);
2629 ixgbe_i2c_start(hw);
2632 ixgbe_i2c_stop(hw);
2637 * @hw: pointer to hardware structure
2641 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2648 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2652 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2666 * @hw: pointer to hardware structure
2669 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2674 if (!on && ixgbe_mng_present(hw))
2677 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2686 if (ixgbe_check_reset_blocked(hw))
2691 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,