Lines Matching refs:hw
37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw);
40 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
44 * @hw: pointer to the HW structure
48 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
50 struct e1000_mac_info *mac = &hw->mac;
86 * @hw: pointer to the HW structure
88 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
96 * @hw: pointer to the HW structure
98 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
106 * @hw: pointer to the HW structure
108 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,
117 * @hw: pointer to the HW structure
119 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
127 * @hw: pointer to the HW structure
129 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,
138 * @hw: pointer to the HW structure
140 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,
149 * @hw: pointer to the HW structure
151 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
160 * @hw: pointer to the HW structure
162 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw,
171 * @hw: pointer to the HW structure
177 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
179 struct e1000_mac_info *mac = &hw->mac;
180 struct e1000_bus_info *bus = &hw->bus;
181 u32 status = E1000_READ_REG(hw, E1000_STATUS);
219 mac->ops.set_lan_id(hw);
226 * @hw: pointer to the HW structure
232 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
234 struct e1000_mac_info *mac = &hw->mac;
235 struct e1000_bus_info *bus = &hw->bus;
243 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
265 mac->ops.set_lan_id(hw);
273 * @hw: pointer to the HW structure
278 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
280 struct e1000_bus_info *bus = &hw->bus;
286 reg = E1000_READ_REG(hw, E1000_STATUS);
292 * @hw: pointer to the HW structure
296 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
298 struct e1000_bus_info *bus = &hw->bus;
302 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
304 status = E1000_READ_REG(hw, E1000_STATUS);
314 * @hw: pointer to the HW structure
318 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
320 struct e1000_bus_info *bus = &hw->bus;
327 * @hw: pointer to the HW structure
332 void e1000_clear_vfta_generic(struct e1000_hw *hw)
339 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
340 E1000_WRITE_FLUSH(hw);
346 * @hw: pointer to the HW structure
353 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
358 E1000_WRITE_FLUSH(hw);
363 * @hw: pointer to the HW structure
370 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
380 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
385 hw->mac.ops.rar_set(hw, mac_addr, i);
390 * @hw: pointer to the HW structure
400 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
409 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
414 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
420 if (hw->mac.type >= e1000_82580)
423 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
435 if (hw->bus.func == E1000_FUNC_1)
437 if (hw->bus.func == E1000_FUNC_2)
440 if (hw->bus.func == E1000_FUNC_3)
444 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
464 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
471 * @hw: pointer to the HW structure
478 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
500 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
501 E1000_WRITE_FLUSH(hw);
502 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
503 E1000_WRITE_FLUSH(hw);
510 * @hw: pointer to the HW structure
516 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
524 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
557 switch (hw->mac.mc_filter_type) {
580 * @hw: pointer to the HW structure
587 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
596 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
600 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
602 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
605 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
610 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
611 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
612 E1000_WRITE_FLUSH(hw);
617 * @hw: pointer to the HW structure
624 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
634 if (hw->bus.type != e1000_bus_type_pcix)
637 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
638 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
648 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
654 * @hw: pointer to the HW structure
658 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
662 E1000_READ_REG(hw, E1000_CRCERRS);
663 E1000_READ_REG(hw, E1000_SYMERRS);
664 E1000_READ_REG(hw, E1000_MPC);
665 E1000_READ_REG(hw, E1000_SCC);
666 E1000_READ_REG(hw, E1000_ECOL);
667 E1000_READ_REG(hw, E1000_MCC);
668 E1000_READ_REG(hw, E1000_LATECOL);
669 E1000_READ_REG(hw, E1000_COLC);
670 E1000_READ_REG(hw, E1000_DC);
671 E1000_READ_REG(hw, E1000_SEC);
672 E1000_READ_REG(hw, E1000_RLEC);
673 E1000_READ_REG(hw, E1000_XONRXC);
674 E1000_READ_REG(hw, E1000_XONTXC);
675 E1000_READ_REG(hw, E1000_XOFFRXC);
676 E1000_READ_REG(hw, E1000_XOFFTXC);
677 E1000_READ_REG(hw, E1000_FCRUC);
678 E1000_READ_REG(hw, E1000_GPRC);
679 E1000_READ_REG(hw, E1000_BPRC);
680 E1000_READ_REG(hw, E1000_MPRC);
681 E1000_READ_REG(hw, E1000_GPTC);
682 E1000_READ_REG(hw, E1000_GORCL);
683 E1000_READ_REG(hw, E1000_GORCH);
684 E1000_READ_REG(hw, E1000_GOTCL);
685 E1000_READ_REG(hw, E1000_GOTCH);
686 E1000_READ_REG(hw, E1000_RNBC);
687 E1000_READ_REG(hw, E1000_RUC);
688 E1000_READ_REG(hw, E1000_RFC);
689 E1000_READ_REG(hw, E1000_ROC);
690 E1000_READ_REG(hw, E1000_RJC);
691 E1000_READ_REG(hw, E1000_TORL);
692 E1000_READ_REG(hw, E1000_TORH);
693 E1000_READ_REG(hw, E1000_TOTL);
694 E1000_READ_REG(hw, E1000_TOTH);
695 E1000_READ_REG(hw, E1000_TPR);
696 E1000_READ_REG(hw, E1000_TPT);
697 E1000_READ_REG(hw, E1000_MPTC);
698 E1000_READ_REG(hw, E1000_BPTC);
703 * @hw: pointer to the HW structure
709 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
711 struct e1000_mac_info *mac = &hw->mac;
729 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
741 e1000_check_downshift_generic(hw);
753 mac->ops.config_collision_dist(hw);
760 ret_val = e1000_config_fc_after_link_up_generic(hw);
769 * @hw: pointer to the HW structure
774 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
776 struct e1000_mac_info *mac = &hw->mac;
784 ctrl = E1000_READ_REG(hw, E1000_CTRL);
785 status = E1000_READ_REG(hw, E1000_STATUS);
786 rxcw = E1000_READ_REG(hw, E1000_RXCW);
805 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
808 ctrl = E1000_READ_REG(hw, E1000_CTRL);
810 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
813 ret_val = e1000_config_fc_after_link_up_generic(hw);
825 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
826 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
836 * @hw: pointer to the HW structure
841 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
843 struct e1000_mac_info *mac = &hw->mac;
851 ctrl = E1000_READ_REG(hw, E1000_CTRL);
852 status = E1000_READ_REG(hw, E1000_STATUS);
853 rxcw = E1000_READ_REG(hw, E1000_RXCW);
870 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
873 ctrl = E1000_READ_REG(hw, E1000_CTRL);
875 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
878 ret_val = e1000_config_fc_after_link_up_generic(hw);
890 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
891 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
894 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
901 rxcw = E1000_READ_REG(hw, E1000_RXCW);
913 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
914 status = E1000_READ_REG(hw, E1000_STATUS);
918 rxcw = E1000_READ_REG(hw, E1000_RXCW);
942 * @hw: pointer to the HW structure
947 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
960 * control setting, then the variable hw->fc will
963 if (hw->mac.type == e1000_i350) {
964 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
965 ret_val = hw->nvm.ops.read(hw,
970 ret_val = hw->nvm.ops.read(hw,
982 hw->fc.requested_mode = e1000_fc_none;
985 hw->fc.requested_mode = e1000_fc_tx_pause;
987 hw->fc.requested_mode = e1000_fc_full;
994 * @hw: pointer to the HW structure
1002 s32 e1000_setup_link_generic(struct e1000_hw *hw)
1011 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
1017 if (hw->fc.requested_mode == e1000_fc_default) {
1018 ret_val = e1000_set_default_fc_generic(hw);
1026 hw->fc.current_mode = hw->fc.requested_mode;
1029 hw->fc.current_mode);
1032 ret_val = hw->mac.ops.setup_physical_interface(hw);
1042 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1043 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1044 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1046 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1048 return e1000_set_fc_watermarks_generic(hw);
1053 * @hw: pointer to the HW structure
1058 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1060 struct e1000_mac_info *mac = &hw->mac;
1081 switch (hw->fc.current_mode) {
1114 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1122 * @hw: pointer to the HW structure
1127 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1129 struct e1000_mac_info *mac = &hw->mac;
1143 status = E1000_READ_REG(hw, E1000_STATUS);
1155 ret_val = mac->ops.check_for_link(hw);
1171 * @hw: pointer to the HW structure
1176 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1183 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1188 hw->mac.ops.config_collision_dist(hw);
1190 ret_val = e1000_commit_fc_settings_generic(hw);
1202 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1203 E1000_WRITE_FLUSH(hw);
1210 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1211 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1212 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1222 * @hw: pointer to the HW structure
1227 static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1233 tctl = E1000_READ_REG(hw, E1000_TCTL);
1238 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1239 E1000_WRITE_FLUSH(hw);
1244 * @hw: pointer to the HW structure
1250 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1262 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1267 fcrtl = hw->fc.low_water;
1268 if (hw->fc.send_xon)
1271 fcrth = hw->fc.high_water;
1273 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1274 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1281 * @hw: pointer to the HW structure
1289 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1295 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1303 * according to the "hw->fc.current_mode" parameter.
1314 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1316 switch (hw->fc.current_mode) {
1336 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1343 * @hw: pointer to the HW structure
1351 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1353 struct e1000_mac_info *mac = &hw->mac;
1366 if (hw->phy.media_type == e1000_media_type_fiber ||
1367 hw->phy.media_type == e1000_media_type_internal_serdes)
1368 ret_val = e1000_force_mac_fc_generic(hw);
1370 if (hw->phy.media_type == e1000_media_type_copper)
1371 ret_val = e1000_force_mac_fc_generic(hw);
1384 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1389 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1392 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1407 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1411 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1457 if (hw->fc.requested_mode == e1000_fc_full) {
1458 hw->fc.current_mode = e1000_fc_full;
1461 hw->fc.current_mode = e1000_fc_rx_pause;
1476 hw->fc.current_mode = e1000_fc_tx_pause;
1490 hw->fc.current_mode = e1000_fc_rx_pause;
1496 hw->fc.current_mode = e1000_fc_none;
1504 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1511 hw->fc.current_mode = e1000_fc_none;
1516 ret_val = e1000_force_mac_fc_generic(hw);
1528 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1533 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1546 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1547 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1590 if (hw->fc.requested_mode == e1000_fc_full) {
1591 hw->fc.current_mode = e1000_fc_full;
1594 hw->fc.current_mode = e1000_fc_rx_pause;
1609 hw->fc.current_mode = e1000_fc_tx_pause;
1623 hw->fc.current_mode = e1000_fc_rx_pause;
1629 hw->fc.current_mode = e1000_fc_none;
1636 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1638 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1640 ret_val = e1000_force_mac_fc_generic(hw);
1652 * @hw: pointer to the HW structure
1659 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1666 status = E1000_READ_REG(hw, E1000_STATUS);
1691 * @hw: pointer to the HW structure
1698 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,
1711 * @hw: pointer to the HW structure
1715 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1718 s32 timeout = hw->nvm.word_size + 1;
1725 swsm = E1000_READ_REG(hw, E1000_SWSM);
1740 swsm = E1000_READ_REG(hw, E1000_SWSM);
1741 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1744 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1752 e1000_put_hw_semaphore_generic(hw);
1762 * @hw: pointer to the HW structure
1766 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1772 swsm = E1000_READ_REG(hw, E1000_SWSM);
1776 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1781 * @hw: pointer to the HW structure
1785 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1792 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1808 * @hw: pointer to the HW structure
1814 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1820 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1834 * @hw: pointer to the HW structure
1837 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1839 struct e1000_mac_info *mac = &hw->mac;
1849 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1853 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1900 * @hw: pointer to the HW structure
1905 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1911 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1914 if (hw->phy.media_type == e1000_media_type_fiber) {
1915 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1916 hw->mac.ledctl_default = ledctl;
1922 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1923 } else if (hw->phy.media_type == e1000_media_type_copper) {
1924 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1932 * @hw: pointer to the HW structure
1937 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1941 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1947 * @hw: pointer to the HW structure
1951 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1958 if (hw->phy.media_type == e1000_media_type_fiber) {
1969 ledctl_blink = hw->mac.ledctl_mode2;
1971 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1973 u32 led_default = hw->mac.ledctl_default >> i;
1987 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1994 * @hw: pointer to the HW structure
1998 s32 e1000_led_on_generic(struct e1000_hw *hw)
2004 switch (hw->phy.media_type) {
2006 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2009 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2012 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2023 * @hw: pointer to the HW structure
2027 s32 e1000_led_off_generic(struct e1000_hw *hw)
2033 switch (hw->phy.media_type) {
2035 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2038 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2041 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2052 * @hw: pointer to the HW structure
2057 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2063 if (hw->bus.type != e1000_bus_type_pci_express)
2067 gcr = E1000_READ_REG(hw, E1000_GCR);
2070 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2076 * @hw: pointer to the HW structure
2085 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2092 if (hw->bus.type != e1000_bus_type_pci_express)
2095 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2097 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2100 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2102 E1000_REMOVED(hw->hw_addr))
2118 * @hw: pointer to the HW structure
2122 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2124 struct e1000_mac_info *mac = &hw->mac;
2140 E1000_WRITE_REG(hw, E1000_AIT, 0);
2145 * @hw: pointer to the HW structure
2150 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2152 struct e1000_mac_info *mac = &hw->mac;
2170 E1000_WRITE_REG(hw, E1000_AIT,
2179 E1000_WRITE_REG(hw, E1000_AIT, 0);
2186 * @hw: pointer to the HW structure
2191 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2195 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2197 hw->phy.mdix = 1;
2206 * @hw: pointer to the HW structure
2211 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2220 * @hw: pointer to the HW structure
2229 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2238 E1000_WRITE_REG(hw, reg, regvalue);
2243 regvalue = E1000_READ_REG(hw, reg);