Lines Matching refs:hw
46 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
47 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
48 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
49 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
51 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
53 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
54 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
55 static s32 e1000_reset_hw_82543(struct e1000_hw *hw);
56 static s32 e1000_init_hw_82543(struct e1000_hw *hw);
57 static s32 e1000_setup_link_82543(struct e1000_hw *hw);
58 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);
59 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);
60 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);
61 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
62 static s32 e1000_led_on_82543(struct e1000_hw *hw);
63 static s32 e1000_led_off_82543(struct e1000_hw *hw);
64 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
66 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
67 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
68 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
69 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
70 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
71 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
72 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
73 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
75 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
76 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
77 static s32 e1000_read_mac_addr_82543(struct e1000_hw *hw);
82 * @hw: pointer to the HW structure
84 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
86 struct e1000_phy_info *phy = &hw->phy;
91 if (hw->phy.media_type != e1000_media_type_copper) {
110 phy->ops.read_reg = (hw->mac.type == e1000_82543)
113 phy->ops.reset = (hw->mac.type == e1000_82543)
116 phy->ops.write_reg = (hw->mac.type == e1000_82543)
126 if (!e1000_init_phy_disabled_82543(hw)) {
127 ret_val = phy->ops.reset(hw);
135 ret_val = e1000_get_phy_id(hw);
140 switch (hw->mac.type) {
165 * @hw: pointer to the HW structure
167 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
169 struct e1000_nvm_info *nvm = &hw->nvm;
191 * @hw: pointer to the HW structure
193 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
195 struct e1000_mac_info *mac = &hw->mac;
200 switch (hw->device_id) {
203 hw->phy.media_type = e1000_media_type_fiber;
206 hw->phy.media_type = e1000_media_type_copper;
223 /* hw initialization */
229 (hw->phy.media_type == e1000_media_type_copper)
233 (hw->phy.media_type == e1000_media_type_copper)
238 (hw->phy.media_type == e1000_media_type_copper)
256 if ((hw->mac.type != e1000_82543) ||
257 (hw->phy.media_type == e1000_media_type_fiber))
258 e1000_set_tbi_compatibility_82543(hw, FALSE);
265 * @hw: pointer to the HW structure
269 void e1000_init_function_pointers_82543(struct e1000_hw *hw)
273 hw->mac.ops.init_params = e1000_init_mac_params_82543;
274 hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
275 hw->phy.ops.init_params = e1000_init_phy_params_82543;
280 * @hw: pointer to the HW structure
285 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
287 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
292 if (hw->mac.type != e1000_82543) {
305 * @hw: pointer to the HW structure
310 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
312 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
316 if (hw->mac.type != e1000_82543) {
332 * @hw: pointer to the HW structure
337 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
339 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
344 if (hw->mac.type != e1000_82543) {
357 * @hw: pointer to the HW structure
362 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
364 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
368 if (state && e1000_tbi_compatibility_enabled_82543(hw))
378 * @hw: pointer to the HW structure
383 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
385 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
390 if (hw->mac.type != e1000_82543) {
403 * @hw: pointer to the HW structure
411 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
415 if (!(e1000_tbi_sbp_enabled_82543(hw)))
481 * @hw: pointer to the HW structure
487 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
505 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
519 mdic = (offset | (hw->phy.addr << 5) |
522 e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
529 *data = e1000_shift_in_mdi_bits_82543(hw);
537 * @hw: pointer to the HW structure
543 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
562 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
571 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
576 e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
584 * @hw: pointer to the HW structure
590 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
596 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
597 E1000_WRITE_FLUSH(hw);
603 * @hw: pointer to the HW structure
609 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
615 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
616 E1000_WRITE_FLUSH(hw);
622 * @hw: pointer to the HW structure
630 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
644 ctrl = E1000_READ_REG(hw, E1000_CTRL);
661 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
662 E1000_WRITE_FLUSH(hw);
666 e1000_raise_mdi_clk_82543(hw, &ctrl);
667 e1000_lower_mdi_clk_82543(hw, &ctrl);
675 * @hw: pointer to the HW structure
682 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
697 ctrl = E1000_READ_REG(hw, E1000_CTRL);
706 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
707 E1000_WRITE_FLUSH(hw);
714 e1000_raise_mdi_clk_82543(hw, &ctrl);
715 e1000_lower_mdi_clk_82543(hw, &ctrl);
719 e1000_raise_mdi_clk_82543(hw, &ctrl);
720 ctrl = E1000_READ_REG(hw, E1000_CTRL);
724 e1000_lower_mdi_clk_82543(hw, &ctrl);
727 e1000_raise_mdi_clk_82543(hw, &ctrl);
728 e1000_lower_mdi_clk_82543(hw, &ctrl);
735 * @hw: pointer to the HW structure
741 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
747 ret_val = e1000_phy_force_speed_duplex_m88(hw);
751 if (!hw->mac.autoneg && (hw->mac.forced_speed_duplex &
753 ret_val = e1000_polarity_reversal_workaround_82543(hw);
761 * @hw: pointer to the HW structure
767 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
774 if (!(hw->phy.ops.write_reg))
781 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
784 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
788 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
802 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
806 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
820 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
824 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
828 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
832 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
836 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
844 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
854 * @hw: pointer to the HW structure
861 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
872 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
875 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
876 E1000_WRITE_FLUSH(hw);
882 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
883 E1000_WRITE_FLUSH(hw);
887 if (!(hw->phy.ops.get_cfg_done))
890 ret_val = hw->phy.ops.get_cfg_done(hw);
897 * @hw: pointer to the HW structure
901 static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
909 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
911 E1000_WRITE_REG(hw, E1000_RCTL, 0);
912 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
913 E1000_WRITE_FLUSH(hw);
915 e1000_set_tbi_sbp_82543(hw, FALSE);
923 ctrl = E1000_READ_REG(hw, E1000_CTRL);
926 if (hw->mac.type == e1000_82543) {
927 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
933 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
940 hw->nvm.ops.reload(hw);
944 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
945 E1000_READ_REG(hw, E1000_ICR);
952 * @hw: pointer to the HW structure
956 static s32 e1000_init_hw_82543(struct e1000_hw *hw)
958 struct e1000_mac_info *mac = &hw->mac;
959 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
967 E1000_WRITE_REG(hw, E1000_VET, 0);
968 mac->ops.clear_vfta(hw);
971 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
976 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
977 E1000_WRITE_FLUSH(hw);
985 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
986 ctrl = E1000_READ_REG(hw, E1000_CTRL);
987 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
990 e1000_pcix_mmrbc_workaround_generic(hw);
993 ret_val = mac->ops.setup_link(hw);
1001 e1000_clear_hw_cntrs_82543(hw);
1008 * @hw: pointer to the HW structure
1019 static s32 e1000_setup_link_82543(struct e1000_hw *hw)
1034 if (hw->mac.type == e1000_82543) {
1035 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1043 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1046 ret_val = e1000_setup_link_generic(hw);
1054 * @hw: pointer to the HW structure
1060 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1068 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1075 if (hw->mac.type == e1000_82543) {
1077 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1078 ret_val = hw->phy.ops.reset(hw);
1083 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1087 ret_val = e1000_copper_link_setup_m88(hw);
1091 if (hw->mac.autoneg) {
1096 ret_val = e1000_copper_link_autoneg(hw);
1105 ret_val = e1000_phy_force_speed_duplex_82543(hw);
1116 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1125 if (hw->mac.type == e1000_82544) {
1126 hw->mac.ops.config_collision_dist(hw);
1128 ret_val = e1000_config_mac_to_phy_82543(hw);
1132 ret_val = e1000_config_fc_after_link_up_generic(hw);
1143 * @hw: pointer to the HW structure
1148 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1155 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1160 hw->mac.ops.config_collision_dist(hw);
1162 ret_val = e1000_commit_fc_settings_generic(hw);
1168 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1169 E1000_WRITE_FLUSH(hw);
1177 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1))
1178 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1188 * @hw: pointer to the HW structure
1197 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1199 struct e1000_mac_info *mac = &hw->mac;
1212 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1221 e1000_check_downshift_generic(hw);
1237 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1238 ret_val = e1000_polarity_reversal_workaround_82543(hw);
1239 icr = E1000_READ_REG(hw, E1000_ICR);
1240 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1241 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1258 hw->mac.ops.config_collision_dist(hw);
1260 ret_val = e1000_config_mac_to_phy_82543(hw);
1273 ret_val = e1000_config_fc_after_link_up_generic(hw);
1285 if (e1000_tbi_compatibility_enabled_82543(hw)) {
1286 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1296 if (e1000_tbi_sbp_enabled_82543(hw)) {
1301 e1000_set_tbi_sbp_82543(hw, FALSE);
1302 rctl = E1000_READ_REG(hw, E1000_RCTL);
1304 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1314 if (!e1000_tbi_sbp_enabled_82543(hw)) {
1315 e1000_set_tbi_sbp_82543(hw, TRUE);
1316 rctl = E1000_READ_REG(hw, E1000_RCTL);
1318 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1328 * @hw: pointer to the HW structure
1333 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1335 struct e1000_mac_info *mac = &hw->mac;
1341 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1342 status = E1000_READ_REG(hw, E1000_STATUS);
1343 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1365 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1368 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1370 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1373 ret_val = e1000_config_fc_after_link_up_generic(hw);
1386 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1387 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1398 * @hw: pointer to the HW structure
1403 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1411 if (!(hw->phy.ops.read_reg))
1415 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1423 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1431 hw->mac.ops.config_collision_dist(hw);
1442 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1450 * @hw: pointer to the HW structure
1457 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1463 if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1464 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1465 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1466 E1000_WRITE_FLUSH(hw);
1467 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1468 E1000_WRITE_FLUSH(hw);
1470 e1000_write_vfta_generic(hw, offset, value);
1476 * @hw: pointer to the HW structure
1480 static s32 e1000_led_on_82543(struct e1000_hw *hw)
1482 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1486 if (hw->mac.type == e1000_82544 &&
1487 hw->phy.media_type == e1000_media_type_copper) {
1496 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1503 * @hw: pointer to the HW structure
1507 static s32 e1000_led_off_82543(struct e1000_hw *hw)
1509 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1513 if (hw->mac.type == e1000_82544 &&
1514 hw->phy.media_type == e1000_media_type_copper) {
1522 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1529 * @hw: pointer to the HW structure
1533 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1537 e1000_clear_hw_cntrs_base_generic(hw);
1539 E1000_READ_REG(hw, E1000_PRC64);
1540 E1000_READ_REG(hw, E1000_PRC127);
1541 E1000_READ_REG(hw, E1000_PRC255);
1542 E1000_READ_REG(hw, E1000_PRC511);
1543 E1000_READ_REG(hw, E1000_PRC1023);
1544 E1000_READ_REG(hw, E1000_PRC1522);
1545 E1000_READ_REG(hw, E1000_PTC64);
1546 E1000_READ_REG(hw, E1000_PTC127);
1547 E1000_READ_REG(hw, E1000_PTC255);
1548 E1000_READ_REG(hw, E1000_PTC511);
1549 E1000_READ_REG(hw, E1000_PTC1023);
1550 E1000_READ_REG(hw, E1000_PTC1522);
1552 E1000_READ_REG(hw, E1000_ALGNERRC);
1553 E1000_READ_REG(hw, E1000_RXERRC);
1554 E1000_READ_REG(hw, E1000_TNCRS);
1555 E1000_READ_REG(hw, E1000_CEXTERR);
1556 E1000_READ_REG(hw, E1000_TSCTC);
1557 E1000_READ_REG(hw, E1000_TSCTFC);
1562 * @hw: pointer to the HW structure
1569 s32 e1000_read_mac_addr_82543(struct e1000_hw *hw)
1578 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
1583 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
1584 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
1588 if (hw->bus.func == E1000_FUNC_1)
1589 hw->mac.perm_addr[5] ^= 1;
1592 hw->mac.addr[i] = hw->mac.perm_addr[i];