dev/e1000/e1000_82543.c

69 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
71 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
585  *  @ctrl: pointer to the control register
590 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
596 	E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
604  *  @ctrl: pointer to the control register
609 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
615 	E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
633 	u32 ctrl, mask;
644 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
647 	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
657 			ctrl |= E1000_CTRL_MDIO;
659 			ctrl &= ~E1000_CTRL_MDIO;
661 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
666 		e1000_raise_mdi_clk_82543(hw, &ctrl);
667 		e1000_lower_mdi_clk_82543(hw, &ctrl);
684 	u32 ctrl;
697 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
703 	ctrl &= ~E1000_CTRL_MDIO_DIR;
704 	ctrl &= ~E1000_CTRL_MDIO;
706 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
714 	e1000_raise_mdi_clk_82543(hw, &ctrl);
715 	e1000_lower_mdi_clk_82543(hw, &ctrl);
719 		e1000_raise_mdi_clk_82543(hw, &ctrl);
720 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
722 		if (ctrl & E1000_CTRL_MDIO)
724 		e1000_lower_mdi_clk_82543(hw, &ctrl);
727 	e1000_raise_mdi_clk_82543(hw, &ctrl);
728 	e1000_lower_mdi_clk_82543(hw, &ctrl);
903 	u32 ctrl;
923 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
927 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
933 		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
960 	u32 ctrl;
986 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
987 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
1062 	u32 ctrl;
1068 	ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1076 		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1077 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1082 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1083 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1150 	u32 ctrl;
1155 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1158 	ctrl &= ~E1000_CTRL_LRST;
1168 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1336 	u32 rxcw, ctrl, status;
1341 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1353 	/* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1354 	if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1368 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
1369 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1370 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1378 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1387 		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1405 	u32 ctrl;
1415 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1416 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1417 	ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1427 	ctrl &= ~E1000_CTRL_FD;
1429 		ctrl |= E1000_CTRL_FD;
1438 		ctrl |= E1000_CTRL_SPD_1000;
1440 		ctrl |= E1000_CTRL_SPD_100;
1442 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1482 	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1489 		ctrl &= ~E1000_CTRL_SWDPIN0;
1490 		ctrl |= E1000_CTRL_SWDPIO0;
1493 		ctrl |= E1000_CTRL_SWDPIN0;
1494 		ctrl |= E1000_CTRL_SWDPIO0;
1496 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1509 	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1516 		ctrl |= E1000_CTRL_SWDPIN0;
1517 		ctrl |= E1000_CTRL_SWDPIO0;
1519 		ctrl &= ~E1000_CTRL_SWDPIN0;
1520 		ctrl |= E1000_CTRL_SWDPIO0;
1522 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);