drm2/radeon/r600_hdmi.c

115 	uint32_t offset = dig->afmt->offset;
117 	WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
118 	WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
120 	WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
121 	WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
123 	WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
124 	WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
170 	uint32_t offset = dig->afmt->offset;
209 	WREG32(HDMI0_AVI_INFO0 + offset,
211 	WREG32(HDMI0_AVI_INFO1 + offset,
213 	WREG32(HDMI0_AVI_INFO2 + offset,
215 	WREG32(HDMI0_AVI_INFO3 + offset,
238 	uint32_t offset = dig->afmt->offset;
256 	WREG32(HDMI0_AUDIO_INFO0 + offset,
258 	WREG32(HDMI0_AUDIO_INFO1 + offset,
271 	uint32_t offset = dig->afmt->offset;
273 	return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
304 	uint32_t offset = dig->afmt->offset;
313 	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
327 	uint32_t offset;
332 	offset = dig->afmt->offset;
336 	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
339 	WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
342 		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
345 		WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
349 		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
356 	WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
360 	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
366 	WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
372 	WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
376 	WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
384 	WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
385 	WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
386 	WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
387 	WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
402 	uint32_t offset;
407 	offset = dig->afmt->offset;
451 	WREG32(HDMI0_60958_0 + offset, iec);
467 	WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
484 	uint32_t offset;
493 	offset = dig->afmt->offset;
521 		WREG32(HDMI0_CONTROL + offset, hdmi);
532 		  offset, radeon_encoder->encoder_id);
544 	uint32_t offset;
555 	offset = dig->afmt->offset;
558 		  offset, radeon_encoder->encoder_id);
584 		WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK);