dev/cxgbe/t4_sge.c

1426 	struct iq_desc *d = &iq->desc[iq->cidx];
1504 			if (__predict_false(++iq->cidx == iq->sidx)) {
1505 				iq->cidx = 0;
1559 	struct iq_desc *d = &iq->desc[iq->cidx];
1658 		if (__predict_false(++iq->cidx == iq->sidx)) {
1659 			iq->cidx = 0;
1766 	struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1856 			return (m);	/* without advancing the cidx */
1859 	if (__predict_false(++fl->cidx % 8 == 0)) {
1860 		uint16_t cidx = fl->cidx / 8;
1862 		if (__predict_false(cidx == fl->sidx))
1863 			fl->cidx = cidx = 0;
1864 		fl->hw_cidx = cidx;
1892 		if (__predict_false(++fl->cidx % 8 == 0)) {
1893 			uint16_t cidx = fl->cidx / 8;
1895 			if (__predict_false(cidx == fl->sidx))
1896 				fl->cidx = cidx = 0;
1897 			fl->hw_cidx = cidx;
2032 		eq->cidx = read_hw_cidx(eq);
2033 		if (eq->pidx == eq->cidx)
2036 			available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2424 	eq->cidx = read_hw_cidx(eq);
2425 	if (eq->pidx == eq->cidx)
2428 		available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2492 			available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2552  * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2556 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2571 	remaining = IDXDIFF(pidx, cidx, r->size);
2577 		while (cidx != pidx) {
2578 			m0 = r->items[cidx];
2580 			if (++cidx == r->size)
2581 				cidx = 0;
2589 	if (eq->pidx == eq->cidx)
2592 		available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2597 		m0 = r->items[cidx];
2607 		next_cidx = cidx + 1;
2621 			/* pkts at cidx, next_cidx should both be in txp. */
2674 		cidx = next_cidx;
2903 	iq->cidx = 0;
2922 		fl->pidx = fl->cidx = 0;
3047 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3048 	    CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I",
3074 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3334 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3346 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3386 	nm_txq->pidx = nm_txq->cidx = 0;
3401 	SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3402 	    CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3424  * Returns a reasonable automatic cidx flush threshold for a given queue size.
3593 	eq->pidx = eq->cidx = eq->dbidx = 0;
3717 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3718 	    CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3811 	SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3812 	    CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3943 	 * before the one with the hw cidx.  This is to avoid hw pidx = hw cidx,
4866 	return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4887 	uint16_t cidx = spg->cidx;	/* stable snapshot */
4889 	return (be16toh(cidx));
4911 		txsd = &txq->sdesc[eq->cidx];
4919 		    ("%s: descriptor with no credits: cidx %d",
4920 		    __func__, eq->cidx));
4929 		IDXINCR(eq->cidx, ndesc, eq->sidx);
4945 		if (eq->cidx == eq->pidx)
5265 		log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5266 		    be16toh(e->u.wr.cidx),
5276 		log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5277 		    be16toh(e->u.acl.cidx),