cxgbe/common/t4_hw.c

3964 	int cause_reg;		/* INT_CAUSE register */
3997 	    alert, ii->name, ii->cause_reg, cause, enable, fatal);
4029 	cause = t4_read_reg(adap, ii->cause_reg);
4030 	if (ii->cause_reg == A_PL_INT_CAUSE)
4049 	t4_write_reg(adap, ii->cause_reg, cause);
4050 	(void)t4_read_reg(adap, ii->cause_reg);
4070 		.cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4091 		.cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4168 		.cause_reg = A_PCIE_INT_CAUSE,
4202 		.cause_reg = A_TP_INT_CAUSE,
4220 		.cause_reg = A_SGE_INT_CAUSE1,
4229 		.cause_reg = A_SGE_INT_CAUSE2,
4309 		.cause_reg = A_SGE_INT_CAUSE3,
4318 		.cause_reg = A_SGE_INT_CAUSE4,
4327 		.cause_reg = A_SGE_INT_CAUSE5,
4336 		.cause_reg = A_SGE_INT_CAUSE6,
4424 		.cause_reg = A_CIM_HOST_INT_CAUSE,
4475 		.cause_reg = A_CIM_HOST_UPACC_INT_CAUSE,
4484 		.cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4537 		.cause_reg = A_ULP_RX_INT_CAUSE,
4546 		.cause_reg = A_ULP_RX_INT_CAUSE_2,
4576 		.cause_reg = A_ULP_TX_INT_CAUSE,
4585 		.cause_reg = A_ULP_TX_INT_CAUSE_2,
4643 		.cause_reg = A_PM_TX_INT_CAUSE,
4683 		.cause_reg = A_PM_RX_INT_CAUSE,
4715 		.cause_reg = A_CPL_INTR_CAUSE,
4773 		.cause_reg = A_LE_DB_INT_CAUSE,
4803 		.cause_reg = A_MPS_RX_PERR_INT_CAUSE,
4823 		.cause_reg = A_MPS_TX_INT_CAUSE,
4838 		.cause_reg = A_MPS_TRC_INT_CAUSE,
4851 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4864 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4877 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4892 		.cause_reg = A_MPS_CLS_INT_CAUSE,
4905 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1,
4959 		ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0);
4965 		ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1);
4972 			ii.cause_reg = A_MC_INT_CAUSE;
4976 			ii.cause_reg = A_MC_P_INT_CAUSE;
4983 		ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1);
5036 		.cause_reg = A_MA_INT_CAUSE,
5045 		.cause_reg = A_MA_PARITY_ERROR_STATUS1,
5054 		.cause_reg = A_MA_PARITY_ERROR_STATUS2,
5085 		.cause_reg = A_SMB_INT_CAUSE,
5110 		.cause_reg = A_NCSI_INT_CAUSE,
5139 		ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
5148 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
5160 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE);
5172 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G);
5193 		.cause_reg = A_PL_PL_INT_CAUSE,
5250 		.cause_reg = A_PL_PERR_CAUSE,
5285 		.cause_reg = A_PL_INT_CAUSE,
5295 	perr = t4_read_reg(adap, pl_perr_cause.cause_reg);
5299 			t4_write_reg(adap, pl_perr_cause.cause_reg, perr);
5369 	static const u32 cause_reg[] = {
5408 	for (i = 0; i < ARRAY_SIZE(cause_reg); i++)
5409 		t4_write_reg(adap, cause_reg[i], 0xffffffff);