ath_hal/ar5212/ar5212_misc.c

21 #include "ah.h"
36 ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac)
38 	struct ath_hal_5212 *ahp = AH5212(ah);
44 ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
46 	struct ath_hal_5212 *ahp = AH5212(ah);
53 ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
55 	struct ath_hal_5212 *ahp = AH5212(ah);
61 ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
63 	struct ath_hal_5212 *ahp = AH5212(ah);
68 	OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
69 	OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
77 ar5212SetRegulatoryDomain(struct ath_hal *ah,
82 	if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
86 	if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
91 	if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
92 		HALDEBUG(ah, HAL_DEBUG_ANY,
95 		AH_PRIVATE(ah)->ah_currentRD = regDomain;
113 ar5212GetWirelessModes(struct ath_hal *ah)
117 	if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
119 		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
121 		if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
123 		if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
126 	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
128 	if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
129 	    AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
131 		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
133 		if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
135 		if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
147 ar5212EnableRfKill(struct ath_hal *ah)
149 	uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
157 	ath_hal_gpioCfgInput(ah, select);
158 	OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000);
167 	ath_hal_gpioSetIntr(ah, select,
168 	    (ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity));
175 ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
189 	bits = OS_REG_READ(ah, AR_PCICFG);
190 	if (IS_2417(ah)) {
207 	OS_REG_WRITE(ah, AR_PCICFG, bits);
217 ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
219 	struct ath_hal_5212 *ahp = AH5212(ah);
224 	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
225 	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
233 ar5212GetTsf64(struct ath_hal *ah)
238 	low1 = OS_REG_READ(ah, AR_TSF_L32);
239 	u32 = OS_REG_READ(ah, AR_TSF_U32);
240 	low2 = OS_REG_READ(ah, AR_TSF_L32);
261 ar5212GetTsf32(struct ath_hal *ah)
263 	return OS_REG_READ(ah, AR_TSF_L32);
267 ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64)
269 	OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
270 	OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
277 ar5212ResetTsf(struct ath_hal *ah)
280 	uint32_t val = OS_REG_READ(ah, AR_BEACON);
282 	OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
290 	OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
299 ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs)
301 	const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
319 	reg = OS_REG_READ(ah, AR_STA_ID1);
321 		OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
323 		OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
331 ar5212GetRandomSeed(struct ath_hal *ah)
335 	nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
338 	return (OS_REG_READ(ah, AR_TSF_U32) ^
339 		OS_REG_READ(ah, AR_TSF_L32) ^ nf);
346 ar5212DetectCardPresent(struct ath_hal *ah)
356 	v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
359 	return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
360 		AH_PRIVATE(ah)->ah_macRev == macRev);
364 ar5212EnableMibCounters(struct ath_hal *ah)
367 	OS_REG_WRITE(ah, AR_MIBC,
372 ar5212DisableMibCounters(struct ath_hal *ah)
374 	OS_REG_WRITE(ah, AR_MIBC,  AR_MIBC | AR_MIBC_CMC);
381 ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats)
383 	stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
384 	stats->rts_bad	  += OS_REG_READ(ah, AR_RTS_FAIL);
385 	stats->fcs_bad	  += OS_REG_READ(ah, AR_FCS_FAIL);
386 	stats->rts_good	  += OS_REG_READ(ah, AR_RTS_OK);
387 	stats->beacons	  += OS_REG_READ(ah, AR_BEACON_CNT);
394 ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah)
403 ar5212GetCurRssi(struct ath_hal *ah)
405 	return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
409 ar5212GetDefAntenna(struct ath_hal *ah)
411 	return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
415 ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna)
417 	OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
421 ar5212GetAntennaSwitch(struct ath_hal *ah)
423 	return AH5212(ah)->ah_antControl;
427 ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting)
429 	struct ath_hal_5212 *ahp = AH5212(ah);
430 	const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
438 	return ar5212SetAntennaSwitchInternal(ah, setting, chan);
442 ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah)
448 ar5212SetSifsTime(struct ath_hal *ah, u_int us)
450 	struct ath_hal_5212 *ahp = AH5212(ah);
452 	if (us > ath_hal_mac_usec(ah, 0xffff)) {
453 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
459 		OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2));
466 ar5212GetSifsTime(struct ath_hal *ah)
468 	u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
469 	return ath_hal_mac_usec(ah, clks)+2;	/* convert from system clocks */
473 ar5212SetSlotTime(struct ath_hal *ah, u_int us)
475 	struct ath_hal_5212 *ahp = AH5212(ah);
477 	if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) {
478 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
484 		OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
491 ar5212GetSlotTime(struct ath_hal *ah)
493 	u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
494 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
498 ar5212SetAckTimeout(struct ath_hal *ah, u_int us)
500 	struct ath_hal_5212 *ahp = AH5212(ah);
502 	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
503 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
509 		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
510 			AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
517 ar5212GetAckTimeout(struct ath_hal *ah)
519 	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
520 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
524 ar5212GetAckCTSRate(struct ath_hal *ah)
526 	return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
530 ar5212SetAckCTSRate(struct ath_hal *ah, u_int high)
532 	struct ath_hal_5212 *ahp = AH5212(ah);
535 		OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
538 		OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
545 ar5212SetCTSTimeout(struct ath_hal *ah, u_int us)
547 	struct ath_hal_5212 *ahp = AH5212(ah);
549 	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
550 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
556 		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
557 			AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
564 ar5212GetCTSTimeout(struct ath_hal *ah)
566 	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
567 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
572 ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
574 	struct ath_hal_5212 *ahp = AH5212(ah);
578         OS_REG_WRITE(ah, AR_DCM_A, keyidx);
579         OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0);
587 ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
592 	AH_PRIVATE(ah)->ah_coverageClass = coverageclass;
595 		if (AH_PRIVATE(ah)->ah_coverageClass == 0)
599 		if (!IEEE80211_IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))
603 		clkRate = ath_hal_mac_clks(ah, 1);
608 		if (IEEE80211_IS_CHAN_HALF(AH_PRIVATE(ah)->ah_curchan)) {
611 		} else if (IEEE80211_IS_CHAN_QUARTER(AH_PRIVATE(ah)->ah_curchan)) {
628 		OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
629 		OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
630 		OS_REG_WRITE(ah, AR_TIME_OUT,
637 ar5212SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration,
640 	OS_REG_WRITE(ah, AR_QUIET2, period | (duration << AR_QUIET2_QUIET_DUR_S));
642 		OS_REG_WRITE(ah, AR_QUIET1, nextStart | (1 << 16));
645 		OS_REG_WRITE(ah, AR_QUIET1, nextStart);
651 ar5212SetPCUConfig(struct ath_hal *ah)
653 	ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
663 ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode)
666 		struct ath_hal_5212 *ahp = AH5212(ah);
667 		return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) &&
681 ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
683 	if (ar5212Use32KHzclock(ah, opmode)) {
689 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
690 		OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
691 		    IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
692 		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
693 		OS_REG_WRITE(ah, AR_TSF_PARM, 61);  /* 32 KHz TSF incr */
694 		OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);
696 		if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) {
697 			OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x26);
698 			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0d);
699 			OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x07);
700 			OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0x3f);
702 			OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);
704 			OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x0a);
705 			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0c);
706 			OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x03);
707 			OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0x20);
708 			OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);
711 		OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);
712 		OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
714 		OS_REG_WRITE(ah, AR_TSF_PARM, 1);	/* 32MHz TSF inc */
716 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
717 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x7f);
719 		if (IS_2417(ah))
720 			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a);
721 		else if (IS_HB63(ah))
722 			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32);
724 			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
725 		OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x0c);
726 		OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0xff);
727 		OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
728 		    IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18);
729 		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
730 		    IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
738 ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
740 	if (ar5212Use32KHzclock(ah, opmode)) {
742 		OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0);
743 		OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
745 		OS_REG_WRITE(ah, AR_TSF_PARM, 1);	/* 32 MHz TSF incr */
746 		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
747 		    IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
752 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
753 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x7f);
754 		OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0e);
755 		OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x0c);
756 		OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0xff);
757 		OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
758 		    IS_RAD5112_ANY(ah) || IS_5413(ah) ?  0x14 : 0x18);
767 ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
793 ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
796 #define	MACVERSION(ah)	AH_PRIVATE(ah)->ah_macVersion
797 	struct ath_hal_5212 *ahp = AH5212(ah);
798 	const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
837 		return MACVERSION(ah) > AR_SREV_VERSION_VENICE ||
838 		    (MACVERSION(ah) == AR_SREV_VERSION_VENICE &&
839 		     AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP;
847 			*result = OS_REG_READ(ah, AR_PHY_RESTART);
853 		*result = AH_PRIVATE(ah)->ah_diagreg;
866 			return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ?
869 			return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) ||
870 			    ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ?
910 			ani = ar5212AniGetCurrentState(ah);
924 		return ath_hal_getcapability(ah, type, capability, result);
930 ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
934 	struct ath_hal_5212 *ahp = AH5212(ah);
935 	const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
954 		OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
963 					v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
968 					OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
977 			v = OS_REG_READ(ah, AR_PHY_RESTART);
980 			OS_REG_WRITE(ah, AR_PHY_RESTART, v);
991 		AH_PRIVATE(ah)->ah_diagreg = setting;
992 		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
1015 		OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC);
1030 			AH5212(ah)->ah_aniControl(ah, cmds[capability], setting) :
1043 		return ath_hal_setcapability(ah, type, capability,
1050 ar5212GetDiagState(struct ath_hal *ah, int request,
1054 	struct ath_hal_5212 *ahp = AH5212(ah);
1058 	if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
1066 		return ath_hal_eepromDiag(ah, request,
1082 		*result = ar5212AniGetCurrentState(ah);
1088 		astats = ar5212AniGetCurrentStats(ah);
1101 		AH5212(ah)->ah_aniControl(ah, ((const uint32_t *)args)[0],
1112 			    ar5212AniGetCurrentState(ah);
1121 			return ar5212AniSetParams(ah, args, args);
1135 ar5212IsNFCalInProgress(struct ath_hal *ah)
1137 	if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
1150 ar5212WaitNFCalComplete(struct ath_hal *ah, int i)
1156 		if (! ar5212IsNFCalInProgress(ah))
1164 ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
1167 	val = OS_REG_READ(ah, AR_PHY_RADAR_0);
1194 	if (IS_5413(ah)) {
1197 			OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1200 			OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
1204 			OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1207 			OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
1211 			OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1214 			OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
1218 			OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1221 			OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
1225 			OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1228 			OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
1232 			OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
1236 			OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
1240 			OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
1244 	OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
1269 ar5212GetDfsDefaultThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
1272 	if (IS_5413(ah)) {
1306 ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
1310 	val = OS_REG_READ(ah, AR_PHY_RADAR_0);
1331 	if (IS_5413(ah)) {
1332 		val = OS_REG_READ(ah, AR_PHY_RADAR_2);
1350 ar5212ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs,
1378 	HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, dur=%d\n",
1396 ar5212IsFastClockEnabled(struct ath_hal *ah)
1406 ar5212Get11nExtBusy(struct ath_hal *ah)
1415 ar5212GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
1417 	struct ath_hal_5212 *ahp = AH5212(ah);
1421 	uint32_t rc = OS_REG_READ(ah, AR_RCCNT);
1422 	uint32_t rf = OS_REG_READ(ah, AR_RFCNT);
1423 	uint32_t tf = OS_REG_READ(ah, AR_TFCNT);
1424 	uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */
1432 		HALDEBUG(ah, HAL_DEBUG_ANY,
1456 ar5212SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask,