contrib/octeon-sdk/cvmx-srxx-defs.h

56 static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id)
59 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
60 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
61 		cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
62 	return CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
68 static inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id)
71 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
72 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
73 		cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id);
74 	return CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
80 static inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
83 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
84 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
85 		cvmx_warn("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
86 	return CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
89 #define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
92 static inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id)
95 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
96 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
97 		cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
98 	return CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
104 static inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id)
107 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
108 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
109 		cvmx_warn("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n", block_id);
110 	return CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
116 static inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id)
119 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
120 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
121 		cvmx_warn("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n", block_id);
122 	return CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull;
125 #define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)