Lines Matching refs:offset

120 static inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset)
123 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
124 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
125 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) ||
126 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 1) && (offset <= 7)))) ||
127 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))) ||
128 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 1) && (offset <= 7)))) ||
129 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 1) && (offset <= 7)))) ||
130 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 1) && (offset <= 7))))))
131 cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n", offset);
132 return CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1;
135 #define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1)
138 static inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset)
141 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
142 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
143 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) ||
144 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 1) && (offset <= 7)))) ||
145 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))) ||
146 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 1) && (offset <= 7)))) ||
147 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 1) && (offset <= 7)))) ||
148 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 1) && (offset <= 7))))))
149 cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n", offset);
150 return CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1;
153 #define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1)
169 static inline uint64_t CVMX_FPA_POOLX_END_ADDR(unsigned long offset)
172 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
173 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
174 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) ||
175 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
176 cvmx_warn("CVMX_FPA_POOLX_END_ADDR(%lu) is invalid on this chip\n", offset);
177 return CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8;
180 #define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8)
183 static inline uint64_t CVMX_FPA_POOLX_START_ADDR(unsigned long offset)
186 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
187 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
188 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) ||
189 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
190 cvmx_warn("CVMX_FPA_POOLX_START_ADDR(%lu) is invalid on this chip\n", offset);
191 return CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8;
194 #define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8)
197 static inline uint64_t CVMX_FPA_POOLX_THRESHOLD(unsigned long offset)
200 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
201 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
202 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
203 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) ||
204 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
205 cvmx_warn("CVMX_FPA_POOLX_THRESHOLD(%lu) is invalid on this chip\n", offset);
206 return CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8;
209 #define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8)
231 static inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset)
234 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
235 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
236 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
237 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
238 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
239 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
241 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
242 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
243 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
244 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) ||
245 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
246 cvmx_warn("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n", offset);
247 return CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8;
250 #define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8)
253 static inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset)
256 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
257 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
258 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
259 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
260 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
261 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
262 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
263 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
264 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
265 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
266 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
267 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
268 cvmx_warn("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n", offset);
269 return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8;
272 #define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8)