Lines Matching defs:ah
19 #include "ah.h"
40 ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level)
42 struct ath_hal_9300 *ahp = AH9300(ah);
46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD &&
55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0);
57 txcfg = OS_REG_READ(ah, AR_TXCFG);
71 OS_REG_WRITE(ah,
76 ar9300_set_interrupts(ah, omask, 0);
78 AH9300(ah)->ah_tx_trig_level = new_level;
87 ar9300_get_tx_trig_level(struct ath_hal *ah)
89 return (AH9300(ah)->ah_tx_trig_level);
97 ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info)
99 struct ath_hal_9300 *ahp = AH9300(ah);
100 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
103 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
106 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info);
113 ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info)
115 struct ath_hal_9300 *ahp = AH9300(ah);
116 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
120 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
123 return ath_hal_getTxQProps(ah, q_info, &ahp->ah_txq[q]);
137 ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type,
140 struct ath_hal_9300 *ahp = AH9300(ah);
142 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
175 HALDEBUG(ah, HAL_DEBUG_QUEUE,
181 HALDEBUG(ah, HAL_DEBUG_QUEUE,
186 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q);
190 HALDEBUG(ah, HAL_DEBUG_QUEUE,
212 (void) ar9300_set_tx_queue_props(ah, q, q_info);
222 set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
224 struct ath_hal_9300 *ahp = AH9300(ah);
226 HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
234 OS_REG_WRITE(ah, AR_IMR_S0,
236 OS_REG_WRITE(ah, AR_IMR_S1,
239 OS_REG_RMW_FIELD(ah,
241 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2);
248 ar9300_release_tx_queue(struct ath_hal *ah, u_int q)
250 struct ath_hal_9300 *ahp = AH9300(ah);
251 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
255 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
261 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
265 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q);
272 set_tx_q_interrupts(ah, qi);
283 ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
285 struct ath_hal_9300 *ahp = AH9300(ah);
286 // struct ath_hal_private *ap = AH_PRIVATE(ah);
287 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
288 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
294 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
300 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
304 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q);
323 if (q > 3 || (!AH9300(ah)->ah_fccaifs))
327 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN)
333 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
342 if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) {
352 OS_REG_WRITE(ah,
363 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
368 OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
417 if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) {
418 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
435 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
441 - ah->ah_config.ah_additional_swba_backoff
442 - ah->ah_config.ah_sw_beacon_response_time
443 + ah->ah_config.ah_dma_beacon_response_time;
450 HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
453 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
493 OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
494 OS_REG_WRITE(ah, AR_QMISC(q), qmisc);
495 OS_REG_WRITE(ah, AR_DMISC(q), dmisc);
527 set_tx_q_interrupts(ah, qi);
536 ar9300_get_tx_dp(struct ath_hal *ah, u_int q)
538 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
539 return OS_REG_READ(ah, AR_QTXDP(q));
546 ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp)
548 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
549 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
552 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
561 ar9300_start_tx_dma(struct ath_hal *ah, u_int q)
571 ar9300_num_tx_pending(struct ath_hal *ah, u_int q)
575 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
577 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
584 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) {
589 if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
590 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
591 HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n");
593 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
598 (AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE));
607 ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout)
609 struct ath_hal_9300 *ahp = AH9300(ah);
621 return ar9300_abort_tx_dma(ah);
628 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
630 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
636 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
639 if (ar9300_num_tx_pending(ah, q) == 0) {
647 HALDEBUG(ah, HAL_DEBUG_QUEUE,
649 HALDEBUG(ah, HAL_DEBUG_QUEUE,
652 OS_REG_READ(ah, AR_QSTS(q)),
653 OS_REG_READ(ah, AR_Q_TXE),
654 OS_REG_READ(ah, AR_Q_TXD),
655 OS_REG_READ(ah, AR_QCBRCFG(q)));
656 HALDEBUG(ah, HAL_DEBUG_QUEUE,
659 OS_REG_READ(ah, AR_QMISC(q)),
660 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
661 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
666 if (ar9300_num_tx_pending(ah, q)) {
669 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
670 __func__, ar9300_num_tx_pending(ah, q), q);
675 tsf_low = OS_REG_READ(ah, AR_TSF_L32);
676 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
677 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
678 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
679 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
681 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
685 HALDEBUG(ah, HAL_DEBUG_QUEUE,
693 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
697 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
701 while (ar9300_num_tx_pending(ah, q)) {
703 HALDEBUG(ah, HAL_DEBUG_TX,
712 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
715 OS_REG_WRITE(ah, AR_Q_TXD, 0);
727 ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout)
733 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
735 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
741 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
744 if (ar9300_num_tx_pending(ah, q) == 0) {
752 HALDEBUG(ah, HAL_DEBUG_QUEUE,
754 HALDEBUG(ah, HAL_DEBUG_QUEUE,
757 OS_REG_READ(ah, AR_QSTS(q)),
758 OS_REG_READ(ah, AR_Q_TXE),
759 OS_REG_READ(ah, AR_Q_TXD),
760 OS_REG_READ(ah, AR_QCBRCFG(q)));
761 HALDEBUG(ah, HAL_DEBUG_QUEUE,
764 OS_REG_READ(ah, AR_QMISC(q)),
765 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
766 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
771 if (ar9300_num_tx_pending(ah, q)) {
774 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
775 __func__, ar9300_num_tx_pending(ah, q), q);
780 tsf_low = OS_REG_READ(ah, AR_TSF_L32);
781 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
782 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
783 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
784 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
786 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
790 HALDEBUG(ah, HAL_DEBUG_QUEUE,
798 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
802 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
806 while (ar9300_num_tx_pending(ah, q)) {
808 HALDEBUG(ah, HAL_DEBUG_TX,
817 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
820 OS_REG_WRITE(ah, AR_Q_TXD, 0);
834 ar9300_abort_tx_dma(struct ath_hal *ah)
836 struct ath_hal_9300 *ahp = AH9300(ah);
846 if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) {
848 stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */
849 ar9300_set_rx_filter(ah, 0);
850 stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */
856 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
862 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
870 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
875 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
877 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
880 nexttbtt = OS_REG_READ(ah, AR_NEXT_TBTT_TIMER);
881 nextdba = OS_REG_READ(ah, AR_NEXT_DMA_BEACON_ALERT);
883 tsf_tbtt = OS_REG_READ(ah, AR_TSF_L32);
886 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, dba);
887 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, tbtt);
888 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
896 if(OS_REG_READ(ah, AR_Q_TXE) == 0) {
902 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n",
914 if (!(ar9300_num_tx_pending(ah, q))) {
921 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
923 q, ar9300_num_tx_pending(ah, q));
929 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, nextdba);
930 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, nexttbtt);
936 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
938 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
940 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
945 OS_REG_WRITE(ah, AR_Q_TXD, 0);
956 ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs)
961 struct ath_hal_9300 *ahp = AH9300(ah);
968 ar9300_reset_tx_status_ring(struct ath_hal *ah)
970 struct ath_hal_9300 *ahp = AH9300(ah);
976 HALDEBUG(ah, HAL_DEBUG_QUEUE,
980 OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start);
981 OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end);
985 ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start,
988 struct ath_hal_9300 *ahp = AH9300(ah);
995 ar9300_reset_tx_status_ring(ah);