ath_hal/ar9300/ar9300_eeprom.c

939 ar9300_selfgen_tpc_reg_write(struct ath_hal *ah, const struct ieee80211_channel *chan,
950     if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1217 int ar9300_get_rx_nf_offset(struct ath_hal *ah, struct ieee80211_channel *chan, int8_t *nf_pwr, int8_t *nf_cal) {
1218     HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2525     const struct ieee80211_channel *chan,
2565     HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2574     ar9300_get_channel_centers(ah, chan, &centers);
2577     if (IEEE80211_IS_CHAN_2GHZ(chan)) {
2584     if (IEEE80211_IS_CHAN_2GHZ(chan)) {
2633     if (IEEE80211_IS_CHAN_2GHZ(chan)) {
2640         if (IEEE80211_IS_CHAN_HT40(chan)) {
2650         if (IEEE80211_IS_CHAN_HT40(chan)) {
2682         if (IEEE80211_IS_CHAN_2GHZ(chan)) {
2693                 "ctl_index 0x%2.2x chan %d chanctl 0x%x\n",
2695                 ichan->channel, ath_hal_getctl(ah, chan));
2710                         p_eep_data, freq, i, IEEE80211_IS_CHAN_2GHZ(chan));
2715                     i, freq, IEEE80211_IS_CHAN_2GHZ(chan),
2896     ar9300_eeprom_t *p_eep_data, const struct ieee80211_channel *chan, u_int16_t cfg_ctl,
2910     HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2970         "%s[%d] +++chan %d,cfgctl 0x%04x  "
2978         if (IEEE80211_IS_CHAN_2GHZ(chan)) {
2979             if (IEEE80211_IS_CHAN_HT40(chan)) {
2989             if (IEEE80211_IS_CHAN_HT40(chan)) {
3000             paprd_scale_factor, p_eep_data, IEEE80211_IS_CHAN_2GHZ(chan), ichan->channel);
3004         if (IEEE80211_IS_CHAN_HT40(chan)) {
3033     ar9300_eeprom_set_power_per_rate_table(ah, p_eep_data, chan,
3040     ahp->reg_dmn = ath_hal_getctl(ah, chan);
3089     ar9300_selfgen_tpc_reg_write(ah, chan, target_power_val_t2);
3122     if (IEEE80211_IS_CHAN_HT40(chan)) {
3124     } else if (IEEE80211_IS_CHAN_HT20(chan)) {
3171         u_int mode = ath_hal_get_curmode(ah, chan);
3178             ar9300_eeprom_set_power_per_rate_table(ah, p_eep_data, chan,
3187             ar9300_init_rate_txpower(ah, mode, chan, target_power_val_t2,
3217 ar9300_eeprom_set_addac(struct ath_hal *ah, struct ieee80211_channel *chan)
3243     p_modal = &(eep->modal_header[IEEE80211_IS_CHAN_2GHZ(chan)]);
3252         ar9300_get_channel_centers(ah, chan, &centers);
3254         reset_freq_bin = FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan));
3277     if (IEEE80211_IS_CHAN_2GHZ(chan)) {
3321   const struct ieee80211_channel *chan,
3326     MODAL_EEPDEF_HEADER *p_modal = &(eep->modal_header[IEEE80211_IS_CHAN_2GHZ(chan)]);
4632 ar9300_eeprom_set_board_values(struct ath_hal *ah, const struct ieee80211_channel *chan)
4634     HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
4636     ar9300_xpa_bias_level_apply(ah, IEEE80211_IS_CHAN_2GHZ(chan));
4638     ar9300_xpa_timing_control_apply(ah, IEEE80211_IS_CHAN_2GHZ(chan));
4640     ar9300_ant_ctrl_apply(ah, IEEE80211_IS_CHAN_2GHZ(chan));
4643     ar9300_x_lNA_bias_strength_apply(ah, IEEE80211_IS_CHAN_2GHZ(chan));