Lines Matching refs:ah
19 #include "ah.h"
55 static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah,
58 static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah);
59 static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah);
60 static inline void ar9300_hw_detach(struct ath_hal *ah);
61 static int16_t ar9300_get_nf_adjust(struct ath_hal *ah,
64 int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp,
69 unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah);
71 static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid);
75 ar9300_disable_pcie_phy(struct ath_hal *ah);
99 int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop)
104 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0);
105 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0);
108 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL);
122 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val );
132 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val);
137 int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters)
143 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0);
149 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1);
157 int ar9300_stop_pcie_error_monitor(struct ath_hal *ah)
162 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL);
172 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val );
558 ar9300_read_revisions(struct ath_hal *ah)
564 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV));
566 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) {
568 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP;
569 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) {
571 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION;
572 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA953X) {
574 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_HONEYBEE;
580 AH_PRIVATE(ah)->ah_macVersion =
593 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) {
599 AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11;
601 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2);
607 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP)
612 AH_PRIVATE(ah)->ah_macRev =
618 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2);
620 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
621 AH_PRIVATE(ah)->ah_ispcie = AH_TRUE;
624 AH_PRIVATE(ah)->ah_ispcie =
639 struct ath_hal *ah;
650 ah = &ahp->ah_priv.h;
651 ar9300_init_offsets(ah, devid);
652 ahpriv = AH_PRIVATE(ah);
653 // AH_PRIVATE(ah)->ah_bustype = bustype;
656 AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE);
657 if (AH9300(ah)->ah_cal_mem == NULL) {
658 ath_hal_printf(ah, "%s: caldata malloc failed!\n", __func__);
667 OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE);
670 ah->ah_config.ath_hal_intr_mitigation_rx = 1;
674 if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) {
680 ah->ah_config.ath_hal_intr_mitigation_rx = 1;
685 if (AR_SREV_HORNET(ah)) {
688 ah->ah_config.ath_hal_intr_mitigation_rx = 0;
693 if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) {
704 ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA));
709 if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */
710 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__);
715 if (AR_SREV_JUPITER(ah)
717 && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14)
723 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val);
727 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
729 ah->ah_btCoexSetWeights = ar9300_mci_bt_coex_set_weights;
730 ah->ah_btCoexDisable = ar9300_mci_bt_coex_disable;
731 ah->ah_btCoexEnable = ar9300_mci_bt_coex_enable;
762 if (AR_SREV_HORNET(ah)) {
764 if (!AR_SREV_HORNET_11(ah)) {
792 if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
809 if (AR_SREV_HONEYBEE(ah)) {
813 ar9300_init_pll(ah, AH_NULL);
815 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
816 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__);
822 ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF;
823 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n",
824 __func__, ah->ah_config.ah_serialise_reg_war);
840 HALDEBUG(ah, HAL_DEBUG_RESET,
849 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
873 HALDEBUG(ah, HAL_DEBUG_RESET,
878 if (AR_SREV_HORNET_12(ah)) {
921 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
936 if (AH9300(ah)->clk_25mhz) {
946 } else if (AR_SREV_HORNET_11(ah)) {
989 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1004 if (AH9300(ah)->clk_25mhz) {
1014 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
1066 if (ah->ah_config.ath_hal_pcie_clock_req) {
1068 if (ah->ah_config.ath_hal_pll_pwr_save
1072 if (ah->ah_config.ath_hal_pll_pwr_save &
1088 if (ah->ah_config.ath_hal_pll_pwr_save &
1119 if (ah->ah_config.ath_hal_pll_pwr_save
1123 if (ah->ah_config.ath_hal_pll_pwr_save &
1139 if (ah->ah_config.ath_hal_pll_pwr_save &
1170 //ah->ah_config.ath_hal_pciePowerSaveEnable = 0;
1171 } else if (AR_SREV_POSEIDON(ah)) {
1223 if (ah->ah_config.ath_hal_pcie_clock_req) {
1225 if (ah->ah_config.ath_hal_pll_pwr_save
1229 if (ah->ah_config.ath_hal_pll_pwr_save &
1245 if (ah->ah_config.ath_hal_pll_pwr_save &
1278 if (ah->ah_config.ath_hal_pll_pwr_save
1282 if (ah->ah_config.ath_hal_pll_pwr_save &
1298 if (ah->ah_config.ath_hal_pll_pwr_save &
1331 /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/
1339 } else if (AR_SREV_WASP(ah)) {
1384 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1409 } else if (AR_SREV_SCORPION(ah)) {
1458 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1469 } else if (AR_SREV_HONEYBEE(ah)) {
1518 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1530 } else if (AR_SREV_JUPITER_10(ah)) {
1575 if (ah->ah_config.ath_hal_pcie_clock_req) {
1602 ah->ah_config.ath_hal_pll_pwr_save = 0;
1604 if (ah->ah_config.ath_hal_pll_pwr_save &
1608 if (ah->ah_config.ath_hal_pll_pwr_save &
1625 if (ah->ah_config.ath_hal_pll_pwr_save &
1663 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1681 else if (AR_SREV_JUPITER_20_OR_LATER(ah)) {
1690 if (AR_SREV_JUPITER_21(ah)) {
1710 if (AR_SREV_JUPITER_21(ah)) {
1733 if (AR_SREV_JUPITER_21(ah)) {
1758 if (ah->ah_config.ath_hal_pcie_clock_req) {
1780 if (ah->ah_config.ath_hal_pll_pwr_save &
1784 if (ah->ah_config.ath_hal_pll_pwr_save &
1801 if (ah->ah_config.ath_hal_pll_pwr_save &
1840 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1857 } else if (AR_SREV_APHRODITE(ah)) {
1911 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1923 } else if (AR_SREV_AR9580(ah)) {
1982 if (ah->ah_config.ath_hal_pcie_clock_req) {
1983 if (ah->ah_config.ath_hal_pll_pwr_save &
1986 if (ah->ah_config.ath_hal_pll_pwr_save &
2009 if (ah->ah_config.ath_hal_pll_pwr_save &
2012 if (ah->ah_config.ath_hal_pll_pwr_save &
2038 if (ah->ah_config.ath_hal_pcie_clock_req) {
2039 if (ah->ah_config.ath_hal_pll_pwr_save &
2042 if (ah->ah_config.ath_hal_pll_pwr_save &
2066 if (ah->ah_config.ath_hal_pll_pwr_save &
2069 if (ah->ah_config.ath_hal_pll_pwr_save &
2093 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
2167 if (ah->ah_config.ath_hal_pcie_clock_req) {
2168 if (ah->ah_config.ath_hal_pll_pwr_save &
2171 if (ah->ah_config.ath_hal_pll_pwr_save &
2205 if (ah->ah_config.ath_hal_pll_pwr_save &
2208 if (ah->ah_config.ath_hal_pll_pwr_save &
2241 if (ah->ah_config.ath_hal_pcie_clock_req) {
2242 if (ah->ah_config.ath_hal_pll_pwr_save &
2245 if (ah->ah_config.ath_hal_pll_pwr_save &
2269 if (ah->ah_config.ath_hal_pll_pwr_save &
2272 if (ah->ah_config.ath_hal_pll_pwr_save &
2296 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
2300 ah->ah_config.ath_hal_pcie_ser_des_write = 1;
2320 if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah))
2326 if (AR_SREV_SCORPION(ah)) {
2329 ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode);
2333 ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP);
2338 ar9300_config_pci_power_save(ah, 0, 0);
2340 ar9300_disable_pcie_phy(ah);
2342 ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__);
2343 ecode = ar9300_hw_attach(ah);
2349 ar9300_tx_gain_table_apply(ah);
2350 ar9300_rx_gain_table_apply(ah);
2357 if (!ar9300_fill_capability_info(ah)) {
2358 HALDEBUG(ah, HAL_DEBUG_RESET,
2363 ecode = ar9300_init_mac_addr(ah);
2365 HALDEBUG(ah, HAL_DEBUG_RESET,
2381 ar9300_wow_set_gpio_reset_low(ah);
2387 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL),
2388 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) |
2390 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG,
2391 AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG)));
2400 if (AR_SREV_HORNET(ah)) {
2408 } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){
2420 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
2434 if (AR_SREV_HORNET(ah)) {
2446 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
2454 } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) {
2462 return ah;
2475 ar9300_detach(struct ath_hal *ah)
2477 HALASSERT(ah != AH_NULL);
2478 HALASSERT(ah->ah_magic == AR9300_MAGIC);
2481 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
2482 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
2487 ar9300_hw_detach(ah);
2488 ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
2490 // ath_hal_hdprintf_deregister(ah);
2492 if (AH9300(ah)->ah_cal_mem)
2493 ath_hal_free(AH9300(ah)->ah_cal_mem);
2494 AH9300(ah)->ah_cal_mem = AH_NULL;
2496 ath_hal_free(ah);
2509 struct ath_hal *ah;
2521 ah = &ahp->ah_priv.h;
2525 ar9300_set_stub_functions(ah);
2528 ar9300_attach_freebsd_ops(ah);
2531 ah->ah_disablePCIE = ar9300_disable_pcie_phy;
2532 AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust;
2533 AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits;
2541 AH_PRIVATE(ah)->amem_handle = amem_handle;
2542 AH_PRIVATE(ah)->ah_osdev = osdev;
2544 ah->ah_sc = sc;
2545 ah->ah_st = st;
2546 ah->ah_sh = sh;
2547 ah->ah_magic = AR9300_MAGIC;
2548 AH_PRIVATE(ah)->ah_devid = devid;
2550 AH_PRIVATE(ah)->ah_flags = 0;
2555 // ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm);
2556 ar9300_config_defaults_freebsd(ah, ah_config);
2561 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM;
2564 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM;
2567 if (ar9300_eep_data_in_flash(ah)) {
2578 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
2579 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */
2584 ah->ah_config.ath_hal_diversity_control;
2586 ah->ah_config.ath_hal_antenna_switch_swap;
2609 ar9300_chip_test(struct ath_hal *ah)
2623 reg_hold[i] = OS_REG_READ(ah, addr);
2626 OS_REG_WRITE(ah, addr, wr_data);
2627 rd_data = OS_REG_READ(ah, addr);
2629 HALDEBUG(ah, HAL_DEBUG_REGIO,
2638 OS_REG_WRITE(ah, addr, wr_data);
2639 rd_data = OS_REG_READ(ah, addr);
2641 HALDEBUG(ah, HAL_DEBUG_REGIO,
2648 OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]);
2658 ar9300_get_channel_edges(struct ath_hal *ah,
2661 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2679 ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn)
2681 AH_PRIVATE(ah)->ah_currentRD = regdmn;
2691 ar9300_fill_capability_info(struct ath_hal *ah)
2694 struct ath_hal_9300 *ahp = AH9300(ah);
2695 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2703 AH_PRIVATE(ah)->ah_currentRD = eeval;
2710 AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT;
2723 ah->ah_config.ath_hal_ht_enable = 1;
2727 ((!ah->ah_config.ath_hal_ht_enable ||
2734 ((!ah->ah_config.ath_hal_ht_enable ||
2788 ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE;
2820 if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
2823 if (AR_SREV_MERLIN(ah)) {
2833 if (AR_SREV_POSEIDON(ah)) {
2846 p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support;
2887 ath_hal_enable_rfkill(ah, AH_TRUE);
2909 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
2911 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI)
2930 if (AR_SREV_JUPITER_20(ah)) {
2945 if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2969 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
3014 if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){
3021 if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) {
3026 if (AR_SREV_POSEIDON(ah)) {
3030 if (AR_SREV_POSEIDON_10(ah)) {
3040 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
3058 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3068 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
3092 ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans,
3095 struct ath_hal_9300 *ahp = AH9300(ah);
3097 return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans);
3103 ar9300_get_chip_power_limits(struct ath_hal *ah,
3123 ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off)
3125 struct ath_hal_9300 *ahp = AH9300(ah);
3128 if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) {
3136 if (AR_SREV_JUPITER(ah)) {
3137 u_int32_t val = ah->ah_config.ath_hal_war70c;
3141 OS_REG_WRITE(ah, 0x570c, val);
3146 if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) {
3153 OS_REG_SET_BIT(ah,
3154 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA);
3160 if (ah->ah_config.ath_hal_pcie_waen) {
3161 OS_REG_WRITE(ah,
3162 AR_HOSTIF_REG(ah, AR_WA),
3163 ah->ah_config.ath_hal_pcie_waen);
3166 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val);
3171 if (ah->ah_config.ath_hal_pcie_ser_des_write) {
3174 OS_REG_WRITE(ah,
3180 OS_REG_WRITE(ah,
3193 ar9300_disable_pcie_phy(struct ath_hal *ah)
3199 ar9300_init_mac_addr(struct ath_hal *ah)
3204 struct ath_hal_9300 *ahp = AH9300(ah);
3215 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n",
3228 ar9300_hw_attach(struct ath_hal *ah)
3232 if (!ar9300_chip_test(ah)) {
3233 HALDEBUG(ah, HAL_DEBUG_REGIO,
3238 ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__);
3239 ecode = ar9300_eeprom_attach(ah);
3240 ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode);
3244 if (!ar9300_rf_attach(ah, &ecode)) {
3245 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n",
3252 ar9300_ani_attach(ah);
3258 ar9300_hw_detach(struct ath_hal *ah)
3261 ar9300_ani_detach(ah);
3265 ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
3271 ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable)
3273 struct ath_hal_9300 *ahp = AH9300(ah);
3287 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
3289 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
3291 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
3293 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
3295 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
3297 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
3300 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3302 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3304 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3306 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3310 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
3313 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
3321 ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp,
3330 struct ath_hal_9300 *ahp = AH9300(ah);
3350 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
3353 if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) {
3357 if (AR9300_IS_RX_IQCAL_DISABLED(ah)) {
3376 ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah)
3378 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
3379 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK)));
3381 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK));
3383 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
3387 return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3);
3389 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
3401 HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz)
3407 ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom;
3408 struct ath_hal_9300 *ahp = AH9300(ah);
3427 if (AR_SREV_AR9580(ah))
3431 switch (ar9300_rx_gain_index_get(ah))
3447 else if (AR_SREV_OSPREY_22(ah))
3450 switch (ar9300_rx_gain_index_get(ah))
3502 HALDEBUG(ah, HAL_DEBUG_RESET,
3518 void ar9300_rx_gain_table_apply(struct ath_hal *ah)
3520 struct ath_hal_9300 *ahp = AH9300(ah);
3521 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
3525 if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah))
3528 if (ar9300_rf_gain_cap_apply(ah, 1))
3532 switch (ar9300_rx_gain_index_get(ah))
3535 if (AR_SREV_JUPITER_10(ah)) {
3541 else if (AR_SREV_JUPITER_20(ah)) {
3556 else if (AR_SREV_JUPITER_21(ah)) {
3573 if (AR_SREV_JUPITER_21(ah)) {
3580 } else if (AR_SREV_JUPITER_20(ah)) {
3591 if (AR_SREV_HORNET_12(ah)) {
3595 } else if (AR_SREV_HORNET_11(ah)) {
3599 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3604 xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio;
3614 ath_hal_gpioCfgOutput(ah, i,
3620 } else if (AR_SREV_POSEIDON(ah)) {
3624 } else if (AR_SREV_JUPITER_10(ah)) {
3628 } else if (AR_SREV_JUPITER_20(ah)) {
3632 } else if (AR_SREV_JUPITER_21(ah)) {
3636 } else if (AR_SREV_AR9580(ah)) {
3640 } else if (AR_SREV_WASP(ah)) {
3644 } else if (AR_SREV_SCORPION(ah)) {
3651 } else if (AR_SREV_HONEYBEE(ah)) {
3665 if (AR_SREV_HORNET_12(ah)) {
3669 } else if (AR_SREV_HORNET_11(ah)) {
3673 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3677 } else if (AR_SREV_POSEIDON(ah)) {
3681 } else if (AR_SREV_JUPITER_10(ah)) {
3686 } else if (AR_SREV_JUPITER_20(ah)) {
3691 } else if (AR_SREV_JUPITER_21(ah)) {
3696 } else if (AR_SREV_APHRODITE(ah)) {
3701 } else if (AR_SREV_AR9580(ah)) {
3705 } else if (AR_SREV_WASP(ah)) {
3709 } else if (AR_SREV_SCORPION(ah)) {
3716 } else if (AR_SREV_HONEYBEE(ah)) {
3732 void ar9300_tx_gain_table_apply(struct ath_hal *ah)
3734 struct ath_hal_9300 *ahp = AH9300(ah);
3736 switch (ar9300_tx_gain_index_get(ah))
3740 if (AR_SREV_HORNET_12(ah)) {
3744 } else if (AR_SREV_HORNET_11(ah)) {
3748 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3752 } else if (AR_SREV_POSEIDON(ah)) {
3756 } else if (AR_SREV_AR9580(ah)) {
3761 } else if (AR_SREV_WASP(ah)) {
3766 } else if (AR_SREV_SCORPION(ah)) {
3771 } else if (AR_SREV_JUPITER_10(ah)) {
3776 } else if (AR_SREV_JUPITER_20(ah)) {
3781 } else if (AR_SREV_JUPITER_21(ah)) {
3786 } else if (AR_SREV_HONEYBEE(ah)) {
3791 } else if (AR_SREV_APHRODITE(ah)) {
3804 if (AR_SREV_HORNET_12(ah)) {
3808 } else if (AR_SREV_HORNET_11(ah)) {
3812 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3816 } else if (AR_SREV_POSEIDON(ah)) {
3820 } else if (AR_SREV_AR9580(ah)) {
3825 } else if (AR_SREV_WASP(ah)) {
3829 } else if (AR_SREV_SCORPION(ah)) {
3833 } else if (AR_SREV_JUPITER_10(ah)) {
3838 } else if (AR_SREV_JUPITER_20(ah)) {
3843 } else if (AR_SREV_JUPITER_21(ah)) {
3848 } else if (AR_SREV_APHRODITE(ah)) {
3853 } else if (AR_SREV_HONEYBEE(ah)) {
3854 if (AR_SREV_HONEYBEE_11(ah)) {
3871 if (AR_SREV_HORNET_12(ah)) {
3875 } else if (AR_SREV_HORNET_11(ah)) {
3879 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3883 } else if (AR_SREV_POSEIDON(ah)) {
3887 } else if (AR_SREV_AR9580(ah)) {
3892 } else if (AR_SREV_WASP(ah)) {
3896 } else if (AR_SREV_APHRODITE(ah)) {
3908 if (AR_SREV_HORNET_12(ah)) {
3912 } else if (AR_SREV_HORNET_11(ah)) {
3916 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3920 } else if (AR_SREV_POSEIDON(ah)) {
3924 } else if (AR_SREV_AR9580(ah)) {
3929 } else if (AR_SREV_WASP(ah)) {
3934 } else if (AR_SREV_APHRODITE(ah)) {
3946 if (AR_SREV_WASP(ah)) {
3951 } else if (AR_SREV_AR9580(ah)) {
3965 if (AR_SREV_POSEIDON(ah)) {
3966 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3979 else if (AR_SREV_WASP(ah)) {
3985 else if (AR_SREV_AR9580(ah)) {
3991 else if (AR_SREV_OSPREY_22(ah)) {
3999 if (AR_SREV_WASP(ah)) {
4006 else if (AR_SREV_POSEIDON(ah)) {
4007 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
4016 else if (AR_SREV_AR9580(ah)) {
4024 if (AR_SREV_WASP(ah)) {
4036 ar9300_ant_div_comb_get_config(struct ath_hal *ah,
4039 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
4046 if (AR_SREV_HORNET_11(ah)) {
4048 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
4061 ar9300_ant_div_comb_set_config(struct ath_hal *ah,
4065 struct ath_hal_9300 *ahp = AH9300(ah);
4068 if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A
4072 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
4093 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val);
4099 ar9300_init_hostif_offsets(struct ath_hal *ah)
4101 AR_HOSTIF_REG(ah, AR_RC) =
4103 AR_HOSTIF_REG(ah, AR_WA) =
4105 AR_HOSTIF_REG(ah, AR_PM_STATE) =
4107 AR_HOSTIF_REG(ah, AR_H_INFOL) =
4109 AR_HOSTIF_REG(ah, AR_H_INFOH) =
4111 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) =
4113 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) =
4115 AR_HOSTIF_REG(ah, AR_EEPROM) =
4117 AR_HOSTIF_REG(ah, AR_SREV) =
4119 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) =
4121 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) =
4123 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) =
4125 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) =
4127 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) =
4129 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) =
4131 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) =
4133 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) =
4135 AR_HOSTIF_REG(ah, AR_PCIE_SERDES) =
4137 AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) =
4139 AR_HOSTIF_REG(ah, AR_GPIO_OUT) =
4141 AR_HOSTIF_REG(ah, AR_GPIO_IN) =
4143 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) =
4145 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) =
4147 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) =
4149 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) =
4151 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) =
4153 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) =
4155 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) =
4157 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) =
4159 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) =
4161 AR_HOSTIF_REG(ah, AR_INPUT_STATE) =
4163 AR_HOSTIF_REG(ah, AR_SPARE) =
4165 AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) =
4167 AR_HOSTIF_REG(ah, AR_CLKRUN) =
4169 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) =
4171 AR_HOSTIF_REG(ah, AR_OBS) =
4173 AR_HOSTIF_REG(ah, AR_RFSILENT) =
4175 AR_HOSTIF_REG(ah, AR_GPIO_PDPU) =
4177 AR_HOSTIF_REG(ah, AR_GPIO_DS) =
4179 AR_HOSTIF_REG(ah, AR_MISC) =
4181 AR_HOSTIF_REG(ah, AR_PCIE_MSI) =
4184 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) =
4186 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) =
4188 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) =
4191 AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) =
4193 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) =
4195 AR_HOSTIF_REG(ah, AR_TXAPSYNC) =
4197 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) =
4199 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) =
4201 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) =
4203 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) =
4205 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) =
4207 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) =
4209 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) =
4214 ar9340_init_hostif_offsets(struct ath_hal *ah)
4216 AR_HOSTIF_REG(ah, AR_RC) =
4218 AR_HOSTIF_REG(ah, AR_WA) =
4220 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) =
4222 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) =
4224 AR_HOSTIF_REG(ah, AR_SREV) =
4226 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) =
4228 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) =
4230 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) =
4232 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) =
4234 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) =
4236 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) =
4238 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) =
4240 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) =
4242 AR_HOSTIF_REG(ah, AR_GPIO_OUT) =
4244 AR_HOSTIF_REG(ah, AR_GPIO_IN) =
4246 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) =
4248 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) =
4250 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) =
4252 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) =
4254 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) =
4256 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) =
4258 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) =
4260 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) =
4262 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) =
4264 AR_HOSTIF_REG(ah, AR_INPUT_STATE) =
4266 AR_HOSTIF_REG(ah, AR_CLKRUN) =
4268 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) =
4270 AR_HOSTIF_REG(ah, AR_OBS) =
4272 AR_HOSTIF_REG(ah, AR_RFSILENT) =
4274 AR_HOSTIF_REG(ah, AR_MISC) =
4276 AR_HOSTIF_REG(ah, AR_PCIE_MSI) =
4278 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) =
4280 AR_HOSTIF_REG(ah, AR_TXAPSYNC) =
4282 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) =
4284 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) =
4286 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) =
4288 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) =
4290 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) =
4292 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) =
4294 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) =
4302 static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid)
4305 ar9340_init_hostif_offsets(ah);
4307 ar9300_init_hostif_offsets(ah);