ath_hal/ar9300/ar9300_attach.c

2662     HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps;
2665         *low = p_cap->halLow5GhzChan;
2666         *high = p_cap->halHigh5GhzChan;
2670         *low = p_cap->halLow2GhzChan;
2671         *high = p_cap->halHigh2GhzChan;
2696     HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps;
2706     p_cap->halSupportsFastClock5GHz = AH_TRUE;
2708     p_cap->halIntrMitigation = AH_TRUE;
2716     p_cap->halWirelessModes = 0;
2726         p_cap->halWirelessModes |= HAL_MODE_11A |
2733         p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G |
2741     p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK);
2742     p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK);
2750     p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask);
2751     p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask);
2759     p_cap->halTkipMicTxRxKeySupport = AH_TRUE;
2761     p_cap->halLow2GhzChan = 2312;
2762     p_cap->halHigh2GhzChan = 2732;
2764     p_cap->halLow5GhzChan = 4920;
2765     p_cap->halHigh5GhzChan = 6100;
2767     p_cap->halCipherCkipSupport = AH_FALSE;
2768     p_cap->halCipherTkipSupport = AH_TRUE;
2769     p_cap->halCipherAesCcmSupport = AH_TRUE;
2771     p_cap->halMicCkipSupport = AH_FALSE;
2772     p_cap->halMicTkipSupport = AH_TRUE;
2773     p_cap->halMicAesCcmSupport = AH_TRUE;
2775     p_cap->halChanSpreadSupport = AH_TRUE;
2776     p_cap->halSleepAfterBeaconBroken = AH_TRUE;
2778     p_cap->halBurstSupport = AH_TRUE;
2779     p_cap->halChapTuningSupport = AH_TRUE;
2780     p_cap->halTurboPrimeSupport = AH_TRUE;
2781     p_cap->halFastFramesSupport = AH_TRUE;
2783     p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G;
2785 //    p_cap->hal_xr_support = AH_FALSE;
2787     p_cap->halHTSupport =
2790     p_cap->halGTTSupport = AH_TRUE;
2791     p_cap->halPSPollBroken = AH_TRUE;    /* XXX fixed in later revs? */
2792     p_cap->halNumMRRetries = 4;		/* Hardware supports 4 MRR */
2793     p_cap->halHTSGI20Support = AH_TRUE;
2794     p_cap->halVEOLSupport = AH_TRUE;
2795     p_cap->halBssIdMaskSupport = AH_TRUE;
2797     p_cap->halMcastKeySrchSupport = AH_TRUE;
2798     p_cap->halTsfAddSupport = AH_TRUE;
2801         p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU);
2803         p_cap->halTotalQueues = HAL_NUM_TX_QUEUES;
2807         p_cap->halKeyCacheSize =
2810         p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE;
2812     p_cap->halFastCCSupport = AH_TRUE;
2813 //    p_cap->hal_num_mr_retries = 4;
2816     p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM;
2821         p_cap->halWowSupport = AH_TRUE;
2822         p_cap->hal_wow_match_pattern_exact = AH_TRUE;
2824             p_cap->hal_wow_pattern_match_dword = AH_TRUE;
2827         p_cap->halWowSupport = AH_FALSE;
2828         p_cap->hal_wow_match_pattern_exact = AH_FALSE;
2831     p_cap->halWowSupport = AH_TRUE;
2832     p_cap->halWowMatchPatternExact = AH_TRUE;
2834         p_cap->halWowMatchPatternExact = AH_TRUE;
2837     p_cap->halCSTSupport = AH_TRUE;
2839     p_cap->halRifsRxSupport = AH_TRUE;
2840     p_cap->halRifsTxSupport = AH_TRUE;
2843     p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX;
2846     p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support;
2848     p_cap->halForcePpmSupport = AH_TRUE;
2849     p_cap->halHwBeaconProcSupport = AH_TRUE;
2863     p_cap->halHasUapsdSupport = AH_FALSE;
2866     p_cap->halNumTxMaps = 4;
2868     p_cap->halTxDescLen = sizeof(struct ar9300_txc);
2869     p_cap->halTxStatusLen = sizeof(struct ar9300_txs);
2870     p_cap->halRxStatusLen = sizeof(struct ar9300_rxs);
2872     p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH;
2873     p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH;
2876     p_cap->halUseCombinedRadarRssi = AH_TRUE;
2877     p_cap->halExtChanDfsSupport = AH_TRUE;
2879     p_cap->halSpectralScanSupport = AH_TRUE;
2888         p_cap->halRfSilentSupport = AH_TRUE;
2892     p_cap->halWpsPushButtonSupport = AH_FALSE;
2895     p_cap->halBtCoexSupport = AH_TRUE;
2896     p_cap->halBtCoexApsmWar = AH_FALSE;
2899     p_cap->halGenTimerSupport = AH_TRUE;
2913             p_cap->halMciSupport = AH_FALSE;
2918             p_cap->halMciSupport = (ahp->ah_enterprise_mode &
2923                  __func__, p_cap->halMciSupport);
2926         p_cap->halMciSupport = AH_FALSE;
2931         p_cap->halRadioRetentionSupport = AH_TRUE;
2933         p_cap->halRadioRetentionSupport = AH_FALSE;
2936     p_cap->halAutoSleepSupport = AH_TRUE;
2938     p_cap->halMbssidAggrSupport = AH_TRUE;
2939 //    p_cap->hal_proxy_sta_support = AH_TRUE;
2942     p_cap->hal4kbSplitTransSupport = AH_FALSE;
2949         p_cap->halRegCap =
2955         p_cap->halRegCap =
2960     p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2962     p_cap->halNumAntCfg5GHz =
2964     p_cap->halNumAntCfg2GHz =
2968     p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */
2970         p_cap->halTxStbcSupport = 0;
2972         p_cap->halTxStbcSupport = 1;
2975     p_cap->halEnhancedDmaSupport = AH_TRUE;
2976     p_cap->halEnhancedDfsSupport = AH_TRUE;
2982     p_cap->halIsrRacSupport = AH_TRUE;
2986     p_cap->hal_wep_tkip_aggr_support = AH_TRUE;
2987     p_cap->hal_wep_tkip_aggr_num_tx_delim = 10;    /* TBD */
2988     p_cap->hal_wep_tkip_aggr_num_rx_delim = 10;    /* TBD */
2989     p_cap->hal_wep_tkip_max_ht_rate = 15;         /* TBD */
2998     p_cap->hal_cfend_fix_support = AH_FALSE;
2999     p_cap->hal_aggr_extra_delim_war = AH_FALSE;
3001     p_cap->halHasLongRxDescTsf = AH_TRUE;
3002 //    p_cap->hal_rx_desc_timestamp_bits = 32;
3003     p_cap->halRxTxAbortSupport = AH_TRUE;
3004     p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL;
3005     p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC;
3008     p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED);
3009     p_cap->halChanHalfRate =
3011     p_cap->halChanQuarterRate =
3016         p_cap->hal49GhzSupport = 1;
3018         p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE);
3024         p_cap->halLDPCSupport = AH_FALSE;
3027             p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/
3031             p_cap->hal_pcie_lcr_extsync_en = AH_TRUE;
3034         p_cap->halLDPCSupport = AH_TRUE;
3038     p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE);
3048                 p_cap->halAntDivCombSupport = AH_TRUE;
3050             p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport;
3059         p_cap->halRxUsingLnaMixing = AH_TRUE;
3065     p_cap->halRxDoMyBeacon = AH_TRUE;
3069         p_cap->hal_wow_gtk_offload_support    = AH_TRUE;
3070         p_cap->hal_wow_arp_offload_support    = AH_TRUE;
3071         p_cap->hal_wow_ns_offload_support     = AH_TRUE;
3072         p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE;
3073         p_cap->hal_wow_acer_magic_support     = AH_TRUE;
3074         p_cap->hal_wow_acer_swka_support      = AH_TRUE;
3076         p_cap->hal_wow_gtk_offload_support    = AH_FALSE;
3077         p_cap->hal_wow_arp_offload_support    = AH_FALSE;
3078         p_cap->hal_wow_ns_offload_support     = AH_FALSE;
3079         p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE;
3080         p_cap->hal_wow_acer_magic_support     = AH_FALSE;
3081         p_cap->hal_wow_acer_swka_support      = AH_FALSE;