freescale/imx/imx6_ccm.c

91 	uint32_t reg;
94 	reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA;
95 	WR4(sc, CCM_CCGR0, reg);
98 	reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT | CCGR1_ECSPI1 |
100 	WR4(sc, CCM_CCGR1, reg);
103 	reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM |
107 	WR4(sc, CCM_CCGR2, reg);
110 	reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG |
112 	WR4(sc, CCM_CCGR3, reg);
115 	reg = CCGR4_PL301_MX6QFAST1_S133 |
117 	WR4(sc, CCM_CCGR4, reg);
120 	reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 |
122 	WR4(sc, CCM_CCGR5, reg);
125 	reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 |
127 	WR4(sc, CCM_CCGR6, reg);
148 	uint32_t reg;
177 	reg = RD4(sc, CCM_CGPR);
178 	reg |= CCM_CGPR_INT_MEM_CLK_LPM;
179 	WR4(sc, CCM_CGPR, reg);
180 	reg = RD4(sc, CCM_CLPCR);
181 	reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN;
182 	WR4(sc, CCM_CLPCR, reg);
215 	uint32_t reg;
224 	reg = RD4(sc, CCM_CSCMR1);
225 	reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S);
226 	reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S);
227 	reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S);
228 	reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S);
229 	reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S);
230 	reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S);
231 	WR4(sc, CCM_CSCMR1, reg);
239 	reg = RD4(sc, CCM_CS1CDR);
241 	reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT);
242 	reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT);
243 	reg |= (0x1 << SSI1_CLK_PODF_SHIFT);
244 	reg |= (0x1 << SSI3_CLK_PODF_SHIFT);
246 	reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT);
247 	reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT);
248 	reg |= (0x3 << SSI1_CLK_PRED_SHIFT);
249 	reg |= (0x3 << SSI3_CLK_PRED_SHIFT);
250 	WR4(sc, CCM_CS1CDR, reg);
253 	reg = RD4(sc, CCM_CS2CDR);
255 	reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT);
256 	reg |= (0x1 << SSI2_CLK_PODF_SHIFT);
258 	reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT);
259 	reg |= (0x3 << SSI2_CLK_PRED_SHIFT);
260 	WR4(sc, CCM_CS2CDR, reg);
398 	uint32_t reg;
401 	reg = RD4(sc, CCM_CCGR3);
403 		reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0;
405 		reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0;
406 	WR4(sc, CCM_CCGR3, reg);
413 	uint32_t reg;
416 	reg = RD4(sc, CCM_CCGR2);
417 	reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR;
418 	WR4(sc, CCM_CCGR2, reg);
421 	reg = RD4(sc, CCM_CHSCCDR);
422 	reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
424 	reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT);
425 	reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT);
426 	WR4(sc, CCM_CHSCCDR, reg);
427 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT);
428 	WR4(sc, CCM_CHSCCDR, reg);