Lines Matching defs:clk
161 struct at91_pmc_clock *clk;
164 clk = at91_pmc_clock_ref("udpck");
165 clk->pmc_mask = PMC_SCER_UDP_SAM9;
166 at91_pmc_clock_deref(clk);
169 clk = at91_pmc_clock_ref("uhpck");
170 clk->pmc_mask = PMC_SCER_UHP_SAM9;
171 at91_pmc_clock_deref(clk);
174 clk = at91_pmc_clock_ref("plla");
175 clk->pll_min_in = SAM9260_PLL_A_MIN_IN_FREQ; /* 1 MHz */
176 clk->pll_max_in = SAM9260_PLL_A_MAX_IN_FREQ; /* 32 MHz */
177 clk->pll_min_out = SAM9260_PLL_A_MIN_OUT_FREQ; /* 80 MHz */
178 clk->pll_max_out = SAM9260_PLL_A_MAX_OUT_FREQ; /* 240 MHz */
179 clk->pll_mul_shift = SAM9260_PLL_A_MUL_SHIFT;
180 clk->pll_mul_mask = SAM9260_PLL_A_MUL_MASK;
181 clk->pll_div_shift = SAM9260_PLL_A_DIV_SHIFT;
182 clk->pll_div_mask = SAM9260_PLL_A_DIV_MASK;
183 clk->set_outb = at91_pll_outa;
184 at91_pmc_clock_deref(clk);
194 clk = at91_pmc_clock_ref("pllb");
195 clk->pll_min_in = SAM9260_PLL_B_MIN_IN_FREQ; /* 1 MHz */
196 clk->pll_max_in = SAM9260_PLL_B_MAX_IN_FREQ; /* 5 MHz */
197 clk->pll_max_in = 2999999; /* ~3 MHz */
198 clk->pll_min_out = SAM9260_PLL_B_MIN_OUT_FREQ; /* 70 MHz */
199 clk->pll_max_out = SAM9260_PLL_B_MAX_OUT_FREQ; /* 130 MHz */
200 clk->pll_mul_shift = SAM9260_PLL_B_MUL_SHIFT;
201 clk->pll_mul_mask = SAM9260_PLL_B_MUL_MASK;
202 clk->pll_div_shift = SAM9260_PLL_B_DIV_SHIFT;
203 clk->pll_div_mask = SAM9260_PLL_B_DIV_MASK;
204 clk->set_outb = at91_pll_outb;
205 at91_pmc_clock_deref(clk);