arm/allwinner/timer.c

92 #define timer_read_4(sc, reg)	\
93 	bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg)
94 #define timer_write_4(sc, reg, val)	\
95 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val)
145 	struct a10_timer_softc *sc;
148 	sc = device_get_softc(dev);
165 	struct a10_timer_softc *sc;
169 	sc = device_get_softc(dev);
171 	if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
176 	sc->sc_dev = dev;
177 	sc->sc_bst = rman_get_bustag(sc->res[0]);
178 	sc->sc_bsh = rman_get_bushandle(sc->res[0]);
181 	err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_hardclock,
182 	    NULL, sc, &sc->sc_ih);
184 		bus_release_resources(dev, a10_timer_spec, sc->res);
191 	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
193 	timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
196 	val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG);
198 	timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val);
200 	sc->timer0_freq = SYS_TIMER_CLKSRC;
203 	sc->et.et_frequency = sc->timer0_freq;
204 	sc->et.et_name = "a10_timer Eventtimer";
205 	sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
206 	sc->et.et_quality = 1000;
207 	sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
208 	sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
209 	sc->et.et_start = a10_timer_timer_start;
210 	sc->et.et_stop = a10_timer_timer_stop;
211 	sc->et.et_priv = sc;
212 	et_register(&sc->et);
215 		arm_set_delay(a10_timer_delay, sc);
216 		a10_timer_sc = sc;
219 	a10_timer_timecounter.tc_frequency = sc->timer0_freq;
223 		device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
225 		device_printf(sc->sc_dev, "event timer clock frequency %u\n",
226 		    sc->timer0_freq);
227 		device_printf(sc->sc_dev, "timecounter clock frequency %lld\n",
238 	struct a10_timer_softc *sc;
242 	sc = (struct a10_timer_softc *)et->et_priv;
245 		sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
247 		sc->sc_period = 0;
251 		count = sc->sc_period;
254 	timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period);
255 	timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count);
257 	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
267 	timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
275 	struct a10_timer_softc *sc;
278 	sc = (struct a10_timer_softc *)et->et_priv;
281 	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
283 	timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
285 	sc->sc_period = 0;
291 a10_timer_get_timerfreq(struct a10_timer_softc *sc)
293 	return (sc->timer0_freq);
299 	struct a10_timer_softc *sc;
302 	sc = (struct a10_timer_softc *)arg;
305 	timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1);
307 	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
314 	if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
316 		timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, sc->sc_period);
320 		timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
323 	if (sc->et.et_active)
324 		sc->et.et_event_cb(&sc->et, sc->et.et_arg);
360 	struct a10_timer_softc *sc = arg;
364 	end = now + (sc->timer0_freq / 1000000) * (usec + 1);