Lines Matching defs:TR
203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
779 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) {
805 .addReg(TR, 0, TSR)
818 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0;
824 TR = RO.getReg(), TSR = RO.getSubReg();
832 if (TR == 0)
833 TR = SR, TSR = SSR;
837 assert(TR || FR);
840 if (TR && FR) {
844 FP.PredR, TR, TSR, FR, FSR);
845 } else if (TR) {
846 MuxR = TR;