Lines Matching defs:RegA
139 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
143 unsigned RegA, unsigned RegB, unsigned Dist);
561 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
562 if (RegA == RegB)
564 if (!RegA || !RegB)
566 return TRI->regsOverlap(RegA, RegB);
627 // -RegB is not tied to a register and RegC is compatible with RegA.
633 // -RegC is not tied to a register and RegB is compatible with RegA.
702 Register RegA = MI->getOperand(DstIdx).getReg();
703 SrcRegMap[RegA] = FromRegC;
712 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
722 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
731 unsigned RegA, unsigned RegB,
765 SrcRegMap.erase(RegA);
1522 Register RegA = DstMO.getReg();
1529 if (RegA == RegB) {
1536 LastCopiedReg = RegA;
1548 MI->getOperand(i).getReg() != RegA);
1553 TII->get(TargetOpcode::COPY), RegA);
1559 if (Register::isVirtualRegister(RegA)) {
1560 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1566 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1580 if (Register::isVirtualRegister(RegA)) {
1581 LiveInterval &LI = LIS->getInterval(RegA);
1600 if (Register::isVirtualRegister(RegA) && Register::isVirtualRegister(RegB))
1601 MRI->constrainRegClass(RegA, RC);
1602 MO.setReg(RegA);
1604 // by SubRegB is compatible with RegA with no subregister. So regardless of
1609 SrcRegMap[RegA] = RegB;