Lines Matching defs:reg
73 hold the reg+offset to use when restoring sp from a frame pointer. */
328 unsigned reg;
339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
1011 struct reg_entry *reg;
1031 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1033 if (!reg)
1037 return reg;
1041 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1052 if (reg && reg->type == REG_TYPE_CN)
1053 return reg->number;
1067 if (reg && reg->type == REG_TYPE_MMXWCG)
1068 return reg->number;
1085 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1088 /* Do not allow a scalar (reg+index) to parse as a register. */
1089 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1092 if (reg && reg->type == type)
1093 return reg->number;
1095 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1253 struct reg_entry *reg = arm_reg_parse_multi (&str);
1264 if (reg == NULL)
1266 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1276 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1278 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1280 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1281 || reg->type == REG_TYPE_NQ))
1283 && (reg->type == REG_TYPE_MMXWCG)))
1284 type = reg->type;
1286 if (type != reg->type)
1289 if (reg->neon)
1290 atype = *reg->neon;
1348 return reg->number;
1353 register (e.g. Neon double or quad reg when either has been requested).
1365 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1367 if (reg == FAIL)
1370 /* Do not allow a scalar (reg+index) to parse as a register. */
1382 return reg;
1395 int reg;
1399 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1401 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1420 return reg * 16 + atype.index;
1444 int reg;
1446 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1456 if (reg <= cur_reg)
1462 for (i = cur_reg + 1; i < reg; i++)
1474 if (range & (1 << reg))
1476 reg);
1477 else if (reg <= cur_reg)
1480 range |= 1 << reg;
1481 cur_reg = reg;
2000 struct reg_entry *reg = insert_reg_alias (str, number, type);
2002 if (!reg)
2010 reg->neon = xmalloc (sizeof (struct neon_typed_alias));
2011 *reg->neon = *atype;
2268 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
2270 if (!reg)
2272 else if (reg->builtin)
2278 free ((char *) reg->name);
2279 if (reg->neon)
2280 free (reg->neon);
2281 free (reg);
3292 s_arm_unwind_save_fpa (int reg)
3322 if (reg == 4)
3331 op = 0xc800 | (reg << 4) | (num_regs - 1);
3394 unsigned int reg;
3397 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3407 if (reg == 8)
3416 op = 0xb300 | (reg << 4) | (count - 1);
3428 int reg;
3439 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3441 if (reg == FAIL)
3447 if (mask >> reg)
3449 mask |= 1 << reg;
3460 else if (reg >= hi_reg)
3465 for (; reg < hi_reg; reg++)
3466 mask |= 1 << reg;
3507 reg = i >> 4;
3510 op = 0xffff << (reg - 1);
3511 if (reg > 0
3512 && ((mask & op) == (1u << (reg - 1))))
3514 op = (1 << (reg + i + 1)) - 1;
3515 op &= ~((1 << reg) - 1);
3526 for (reg = 15; reg >= -1; reg--)
3529 if (reg < 0
3530 || !(mask & (1 << reg)))
3532 /* We found an unsaved reg. Generate opcodes to save the
3534 if (reg != hi_reg)
3536 if (reg == 9)
3545 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3549 hi_reg = reg - 1;
3561 int reg;
3571 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3573 if (reg == FAIL)
3579 reg -= 8;
3580 if (mask >> reg)
3582 mask |= 1 << reg;
3593 else if (reg >= hi_reg)
3598 for (; reg < hi_reg; reg++)
3599 mask |= 1 << reg;
3613 for (reg = 0; reg < 16; reg++)
3615 if (mask & (1 << reg))
3633 struct reg_entry *reg;
3645 reg = arm_reg_parse_multi (&peek);
3647 if (!reg)
3654 switch (reg->type)
3663 s_arm_unwind_save_fpa (reg->number);
3688 int reg;
3692 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3693 if (reg == FAIL)
3711 if (reg == REG_SP || reg == REG_PC)
3721 op = 0x90 | reg;
3725 unwind.fp_reg = reg;
3771 as_bad (_("expected <reg>, <reg>"));
4022 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4033 32 bits in reg, in a (hopefully) portable way. */
4039 inst.operands[i].reg = 0;
4041 inst.operands[i].reg |= generic_bignum[idx]
4257 int reg;
4316 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4318 inst.operands[i].imm = reg;
4349 inst.operands[i].reg = value;
4568 [Rn, #offset] .reg=Rn .reloc.exp=offset
4569 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4570 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4577 [Rn], #offset .reg=Rn .reloc.exp=offset
4578 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4579 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4584 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4590 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4600 int reg;
4608 inst.operands[i].reg = REG_PC;
4621 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
4626 inst.operands[i].reg = reg;
4636 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4638 inst.operands[i].imm = reg;
4789 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4794 inst.operands[i].imm |= reg;
4796 inst.operands[i].imm = reg;
5095 int reg;
5103 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5108 inst.operands[0].reg = reg;
5116 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5121 inst.operands[0].imm = reg;
5162 inst.operands[i].reg = val;
5173 inst.operands[i].reg = val;
5184 inst.operands[i].reg = val;
5196 inst.operands[i].reg = val;
5212 inst.operands[i].reg = val;
5225 inst.operands[i].reg = val;
5241 inst.operands[i].reg = val;
5251 inst.operands[i].reg = val;
5275 inst.operands[i].reg = val;
5285 inst.operands[i].reg = val;
5293 inst.operands[i].reg = val;
5307 inst.operands[i].reg = val;
5326 inst.operands[i].reg = val;
5338 inst.operands[i].reg = val;
5406 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
5407 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
5408 OP_RR_RNSC, /* ARM reg or Neon scalar. */
5409 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
5410 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
5411 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
5413 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */
5414 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
5461 OP_RIWR_RIWC, /* iWMMXt R or C reg */
5462 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
5514 inst.operands[i].reg = val; \
5529 inst.operands[i].reg = val; \
5548 inst.operands[i].reg = val; \
5847 inst.operands[i].reg = val;
5866 inst.operands[i].reg = rege->number;
5881 inst.operands[i].reg = rege->number;
5896 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
5944 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
5948 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
5953 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5958 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5965 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5970 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6030 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6167 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6170 && reg > 15)
6191 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6195 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6199 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6203 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6207 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6211 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6244 inst.instruction |= inst.operands[i].reg;
6256 inst.instruction |= inst.operands[i].reg << 16;
6364 inst.instruction |= inst.operands[i].reg << 16;
6386 if (inst.operands[i].reg == REG_PC)
6450 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
6484 inst.operands[1].reg = REG_PC;
6508 inst.instruction |= inst.operands[0].reg << 12;
6514 inst.instruction |= inst.operands[0].reg << 12;
6515 inst.instruction |= inst.operands[1].reg;
6521 inst.instruction |= inst.operands[0].reg << 12;
6522 inst.instruction |= inst.operands[1].reg << 16;
6528 inst.instruction |= inst.operands[0].reg << 16;
6529 inst.instruction |= inst.operands[1].reg << 12;
6535 unsigned Rn = inst.operands[2].reg;
6538 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
6540 inst.instruction |= inst.operands[0].reg << 12;
6541 inst.instruction |= inst.operands[1].reg;
6548 inst.instruction |= inst.operands[0].reg << 12;
6549 inst.instruction |= inst.operands[1].reg << 16;
6550 inst.instruction |= inst.operands[2].reg;
6556 inst.instruction |= inst.operands[0].reg;
6557 inst.instruction |= inst.operands[1].reg << 12;
6558 inst.instruction |= inst.operands[2].reg << 16;
6570 inst.instruction |= inst.operands[0].reg << 12;
6584 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6601 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6615 inst.operands[1].reg = inst.operands[0].reg;
6616 inst.instruction |= inst.operands[0].reg << 12;
6617 inst.instruction |= inst.operands[1].reg << 16;
6643 inst.instruction |= inst.operands[0].reg << 12;
6656 inst.operands[1].reg = REG_PC;
6662 inst.instruction |= inst.operands[0].reg << 12;
6663 inst.instruction |= inst.operands[1].reg;
6673 inst.instruction |= inst.operands[0].reg << 12;
6674 inst.instruction |= inst.operands[1].reg;
6753 if (inst.operands[0].reg == REG_PC)
6756 inst.instruction |= inst.operands[0].reg;
6776 if (inst.operands[0].reg == REG_PC)
6779 inst.instruction |= inst.operands[0].reg;
6788 if (inst.operands[0].reg == REG_PC)
6791 inst.instruction |= inst.operands[0].reg;
6800 inst.instruction |= inst.operands[0].reg << 8;
6802 inst.instruction |= inst.operands[2].reg << 12;
6803 inst.instruction |= inst.operands[3].reg << 16;
6804 inst.instruction |= inst.operands[4].reg;
6811 inst.instruction |= inst.operands[0].reg << 16;
6826 inst.instruction |= inst.operands[0].reg << 8;
6832 inst.instruction |= inst.operands[2].reg << 12;
6833 inst.instruction |= inst.operands[3].reg << 16;
6834 inst.instruction |= inst.operands[4].reg;
6854 inst.instruction |= inst.operands[0].reg << 8;
6856 inst.instruction |= inst.operands[2].reg << 12;
6857 inst.instruction |= inst.operands[3].reg << 16;
6858 inst.instruction |= inst.operands[4].reg;
6889 int base_reg = inst.operands[0].reg;
6908 /* Only allowed if base reg not in list for other types. */
6917 /* Only allowed if base reg not in list, or first in list. */
6920 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6934 constraint (inst.operands[0].reg % 2 != 0,
6937 && inst.operands[1].reg != inst.operands[0].reg + 1,
6939 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6943 inst.operands[1].reg = inst.operands[0].reg + 1;
6951 if (inst.operands[2].reg == inst.operands[1].reg
6959 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
6960 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
6964 inst.instruction |= inst.operands[0].reg << 12;
6986 || (inst.operands[1].reg == REG_PC),
6993 inst.instruction |= inst.operands[0].reg << 12;
6994 inst.instruction |= inst.operands[1].reg << 16;
7001 constraint (inst.operands[0].reg % 2 != 0,
7004 && inst.operands[1].reg != inst.operands[0].reg + 1,
7008 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7010 inst.instruction |= inst.operands[0].reg << 12;
7011 inst.instruction |= inst.operands[2].reg << 16;
7017 inst.instruction |= inst.operands[0].reg << 12;
7039 inst.instruction |= inst.operands[0].reg << 12;
7048 inst.instruction |= inst.operands[0].reg << 12;
7070 inst.instruction |= inst.operands[0].reg << 12;
7079 inst.instruction |= inst.operands[0].reg << 8;
7080 inst.instruction |= inst.operands[1].reg << 12;
7088 if (inst.operands[0].reg == inst.operands[1].reg
7093 inst.instruction |= inst.operands[0].reg << 16;
7094 inst.instruction |= inst.operands[1].reg;
7095 inst.instruction |= inst.operands[2].reg << 8;
7096 inst.instruction |= inst.operands[3].reg << 12;
7102 inst.instruction |= inst.operands[0].reg << 12;
7118 inst.instruction |= inst.operands[0].reg << 12;
7135 if (inst.operands[1].reg != 1)
7166 if (inst.operands[0].reg > 14)
7173 if (thumb_mode && inst.operands[0].reg == REG_SP)
7180 if (inst.operands[0].isvec && inst.operands[1].reg != 1)
7189 rt = inst.operands[0].reg;
7193 inst.instruction |= inst.operands[1].reg << 16;
7200 if (inst.operands[1].reg > 14)
7207 if (thumb_mode && inst.operands[0].reg == REG_SP)
7214 inst.instruction |= inst.operands[1].reg << 12;
7215 inst.instruction |= inst.operands[0].reg << 16;
7228 inst.instruction |= inst.operands[0].reg << 12;
7244 inst.instruction |= inst.operands[1].reg;
7257 inst.operands[2].reg = inst.operands[0].reg;
7258 inst.instruction |= inst.operands[0].reg << 16;
7259 inst.instruction |= inst.operands[1].reg;
7260 inst.instruction |= inst.operands[2].reg << 8;
7262 if (inst.operands[0].reg == inst.operands[1].reg
7276 inst.instruction |= inst.operands[0].reg << 12;
7277 inst.instruction |= inst.operands[1].reg << 16;
7278 inst.instruction |= inst.operands[2].reg;
7279 inst.instruction |= inst.operands[3].reg << 8;
7282 if (inst.operands[0].reg == inst.operands[1].reg
7283 || ((inst.operands[0].reg == inst.operands[2].reg
7284 || inst.operands[1].reg == inst.operands[2].reg)
7308 inst.instruction |= inst.operands[0].reg << 12;
7309 inst.instruction |= inst.operands[1].reg << 16;
7310 inst.instruction |= inst.operands[2].reg;
7325 inst.instruction |= inst.operands[0].reg << 12;
7326 inst.instruction |= inst.operands[1].reg;
7327 inst.instruction |= inst.operands[2].reg << 16;
7331 inst.instruction |= inst.operands[0].reg << 12;
7332 inst.instruction |= inst.operands[1].reg << 16;
7333 inst.instruction |= inst.operands[2].reg;
7381 inst.operands[0].reg = REG_SP;
7394 inst.instruction |= inst.operands[0].reg << 16;
7404 inst.instruction |= inst.operands[0].reg << 12;
7406 inst.instruction |= inst.operands[2].reg;
7417 inst.instruction |= inst.operands[0].reg << 12;
7419 inst.instruction |= inst.operands[2].reg;
7430 inst.instruction |= inst.operands[0].reg << 12;
7432 inst.instruction |= inst.operands[2].reg;
7438 inst.instruction |= inst.operands[0].reg << 12;
7440 inst.instruction |= inst.operands[2].reg;
7460 ? inst.operands[1].reg
7461 : inst.operands[0].reg);
7463 inst.instruction |= inst.operands[0].reg << 12;
7467 inst.instruction |= inst.operands[2].reg << 8;
7496 inst.instruction |= inst.operands[0].reg << 16;
7497 inst.instruction |= inst.operands[1].reg;
7498 inst.instruction |= inst.operands[2].reg << 8;
7499 inst.instruction |= inst.operands[3].reg << 12;
7510 inst.instruction |= inst.operands[0].reg << 12;
7511 inst.instruction |= inst.operands[1].reg << 16;
7512 inst.instruction |= inst.operands[2].reg;
7513 inst.instruction |= inst.operands[3].reg << 8;
7515 if (inst.operands[0].reg == inst.operands[1].reg)
7526 inst.instruction |= inst.operands[0].reg << 16;
7527 inst.instruction |= inst.operands[1].reg;
7528 inst.instruction |= inst.operands[2].reg << 8;
7537 int reg;
7541 reg = inst.operands[0].reg;
7542 constraint (reg != 13, _("SRS base register must be r13"));
7545 reg = 13;
7547 inst.instruction |= reg << 16;
7563 || (inst.operands[2].reg == REG_PC),
7566 constraint (inst.operands[0].reg == inst.operands[1].reg
7567 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
7573 inst.instruction |= inst.operands[0].reg << 12;
7574 inst.instruction |= inst.operands[1].reg;
7575 inst.instruction |= inst.operands[2].reg << 16;
7582 constraint (inst.operands[1].reg % 2 != 0,
7585 && inst.operands[2].reg != inst.operands[1].reg + 1,
7589 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
7591 constraint (inst.operands[0].reg == inst.operands[1].reg
7592 || inst.operands[0].reg == inst.operands[1].reg + 1
7593 || inst.operands[0].reg == inst.operands[3].reg,
7596 inst.instruction |= inst.operands[0].reg << 12;
7597 inst.instruction |= inst.operands[1].reg;
7598 inst.instruction |= inst.operands[3].reg << 16;
7612 inst.instruction |= inst.operands[0].reg << 12;
7613 inst.instruction |= inst.operands[1].reg << 16;
7614 inst.instruction |= inst.operands[2].reg;
7627 inst.instruction |= inst.operands[0].reg << 12;
7628 inst.instruction |= inst.operands[1].reg;
7639 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7640 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7646 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7647 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7648 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7654 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7660 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7661 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7667 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7668 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7674 inst.instruction |= inst.operands[0].reg << 12;
7675 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7683 inst.instruction |= inst.operands[0].reg << 12;
7684 inst.instruction |= inst.operands[1].reg << 16;
7685 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7691 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
7692 inst.instruction |= inst.operands[1].reg << 12;
7700 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
7701 inst.instruction |= inst.operands[1].reg << 12;
7702 inst.instruction |= inst.operands[2].reg << 16;
7708 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7715 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7728 inst.instruction |= inst.operands[0].reg << 16;
7729 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
7744 inst.instruction |= inst.operands[0].reg << 16;
7745 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7793 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7794 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7800 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
7801 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7807 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7808 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7814 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7815 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7816 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
7822 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7828 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
7829 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7830 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
7837 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7845 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7861 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7868 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7875 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7882 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7893 inst.instruction |= inst.operands[0].reg << 16;
7894 inst.instruction |= inst.operands[1].reg;
7900 inst.instruction |= inst.operands[0].reg << 12;
7943 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
7949 inst.instruction |= inst.operands[0].reg << 12;
7956 inst.instruction |= inst.operands[0].reg << 12;
7957 inst.instruction |= inst.operands[1].reg << 16;
7964 inst.instruction |= inst.operands[0].reg << 16;
7965 inst.instruction |= inst.operands[1].reg << 12;
7972 inst.instruction |= inst.operands[0].reg << 5;
7973 inst.instruction |= inst.operands[1].reg;
7974 inst.instruction |= inst.operands[2].reg << 12;
7980 inst.instruction |= inst.operands[0].reg << 12;
7981 inst.instruction |= inst.operands[1].reg << 16;
7982 inst.instruction |= inst.operands[2].reg;
7989 inst.instruction |= inst.operands[0].reg << 12;
7990 inst.instruction |= inst.operands[1].reg << 16;
7991 inst.instruction |= inst.operands[2].reg;
7999 inst.instruction |= inst.operands[0].reg << 12;
8000 inst.instruction |= inst.operands[1].reg << 16;
8001 inst.instruction |= inst.operands[1].reg;
8008 inst.instruction |= inst.operands[0].reg << 12;
8026 inst.instruction |= inst.operands[0].reg << 12;
8033 inst.instruction |= inst.operands[0].reg << 12;
8045 inst.instruction |= inst.operands[1].reg << 16;
8056 inst.instruction |= inst.operands[0].reg << 12;
8057 inst.instruction |= inst.operands[1].reg << 16;
8065 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8066 inst.instruction |= inst.operands[0].reg;
8067 inst.instruction |= inst.operands[0].reg << 12;
8068 inst.instruction |= inst.operands[0].reg << 16;
8130 inst.instruction |= inst.operands[0].reg << 16;
8131 inst.instruction |= inst.operands[1].reg;
8132 inst.instruction |= inst.operands[2].reg << 12;
8141 inst.instruction |= inst.operands[0].reg << 5;
8142 inst.instruction |= inst.operands[1].reg << 12;
8143 inst.instruction |= inst.operands[2].reg << 16;
8144 inst.instruction |= inst.operands[3].reg;
8151 inst.instruction |= inst.operands[1].reg << 12;
8163 inst.instruction |= inst.operands[0].reg << 12;
8164 inst.instruction |= inst.operands[1].reg << 16;
8185 inst.instruction |= inst.operands[1].reg;
8186 inst.instruction |= inst.operands[2].reg << 12;
8196 inst.instruction |= inst.operands[1].reg << 12;
8197 inst.instruction |= inst.operands[2].reg << 16;
8207 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
8208 inst.instruction |= inst.operands[0].reg << 12;
8209 inst.instruction |= inst.operands[1].reg << 16;
8226 inst.instruction |= inst.operands[i].reg;
8260 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8265 inst.instruction |= inst.operands[i].reg << 16;
8440 Rd = inst.operands[0].reg;
8441 Rn = inst.operands[1].reg;
8456 Rd = inst.operands[0].reg;
8458 ? inst.operands[1].reg /* Rd, Rs, foo */
8459 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8547 Rn = inst.operands[2].reg;
8613 Rn = inst.operands[2].reg;
8643 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
8648 inst.instruction |= inst.operands[0].reg << 4;
8654 inst.instruction |= inst.operands[0].reg << 8;
8666 inst.instruction |= inst.operands[0].reg << 4;
8681 Rd = inst.operands[0].reg;
8683 ? inst.operands[1].reg /* Rd, Rs, foo */
8684 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8685 Rn = inst.operands[2].reg;
8764 Rd = inst.operands[0].reg;
8766 ? inst.operands[1].reg /* Rd, Rs, foo */
8767 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8768 Rn = inst.operands[2].reg;
8871 inst.instruction |= inst.operands[0].reg << 8;
8885 inst.operands[1].reg = REG_PC;
8891 inst.instruction |= inst.operands[0].reg << 8;
8892 inst.instruction |= inst.operands[1].reg << 16;
8903 inst.instruction |= inst.operands[0].reg << 8;
8904 inst.instruction |= inst.operands[1].reg << 16;
8926 inst.instruction |= inst.operands[0].reg << 3;
9029 inst.instruction |= inst.operands[0].reg << 3;
9030 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9039 if (inst.operands[0].reg == REG_PC)
9042 inst.instruction |= inst.operands[0].reg << 16;
9048 inst.instruction |= inst.operands[0].reg << 8;
9049 inst.instruction |= inst.operands[1].reg << 16;
9050 inst.instruction |= inst.operands[1].reg;
9096 inst.instruction |= inst.operands[0].reg << 8;
9097 inst.instruction |= inst.operands[1].reg;
9101 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9102 inst.instruction |= (inst.operands[0].reg & 0x7);
9103 inst.instruction |= inst.operands[1].reg << 3;
9111 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9112 inst.instruction |= inst.operands[0].reg;
9127 inst.operands[1].reg = inst.operands[0].reg;
9128 inst.instruction |= inst.operands[0].reg << 8;
9129 inst.instruction |= inst.operands[1].reg << 16;
9130 inst.instruction |= inst.operands[2].reg;
9254 mask = 1 << inst.operands[0].reg;
9256 if (inst.operands[0].reg <= 7
9266 inst.operands[0].reg);
9269 inst.instruction |= inst.operands[0].reg << 8;
9273 else if (inst.operands[0] .reg == REG_SP
9288 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
9294 constraint (inst.operands[0].reg > 7
9303 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
9304 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
9306 inst.operands[0].reg);
9311 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
9314 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
9319 inst.instruction |= inst.operands[0].reg << 8;
9333 inst.instruction |= inst.operands[0].reg << 12;
9334 inst.instruction |= inst.operands[1].reg << 16;
9343 constraint (inst.operands[0].reg == REG_LR,
9346 inst.operands[1].reg = inst.operands[0].reg + 1;
9348 constraint (inst.operands[0].reg == inst.operands[1].reg,
9351 inst.instruction |= inst.operands[0].reg << 12;
9352 inst.instruction |= inst.operands[1].reg << 8;
9353 inst.instruction |= inst.operands[2].reg << 16;
9375 && !inst.operands[1].negative && inst.operands[0].reg <= 7
9380 Rn = inst.operands[1].reg;
9410 inst.instruction = inst.operands[0].reg << 8;
9414 inst.instruction = inst.operands[0].reg;
9415 inst.instruction |= inst.operands[1].reg << 3;
9427 inst.instruction |= inst.operands[0].reg << 12;
9432 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9437 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
9455 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
9459 constraint (inst.operands[1].reg == REG_PC
9465 if (inst.operands[1].reg == REG_PC)
9472 inst.instruction |= inst.operands[0].reg << 8;
9477 constraint (inst.operands[1].reg > 7, BAD_HIREG);
9481 inst.instruction |= inst.operands[0].reg;
9482 inst.instruction |= inst.operands[1].reg << 3;
9506 inst.instruction |= inst.operands[0].reg;
9507 inst.instruction |= inst.operands[1].reg << 3;
9516 inst.operands[1].reg = inst.operands[0].reg + 1;
9517 constraint (inst.operands[0].reg == REG_LR,
9520 inst.instruction |= inst.operands[0].reg << 12;
9521 inst.instruction |= inst.operands[1].reg << 8;
9529 inst.instruction |= inst.operands[0].reg << 12;
9536 inst.instruction |= inst.operands[0].reg << 8;
9537 inst.instruction |= inst.operands[1].reg << 16;
9538 inst.instruction |= inst.operands[2].reg;
9539 inst.instruction |= inst.operands[3].reg << 12;
9545 inst.instruction |= inst.operands[0].reg << 12;
9546 inst.instruction |= inst.operands[1].reg << 8;
9547 inst.instruction |= inst.operands[2].reg << 16;
9548 inst.instruction |= inst.operands[3].reg;
9562 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
9575 && inst.operands[0].reg == REG_PC
9576 && inst.operands[1].reg == REG_LR)
9590 inst.instruction |= inst.operands[0].reg << 8;
9600 inst.instruction |= inst.operands[0].reg << r0off;
9622 if (inst.operands[0].reg != inst.operands[1].reg)
9646 inst.instruction |= inst.operands[0].reg;
9654 inst.instruction |= inst.operands[0].reg << 8;
9655 inst.instruction |= inst.operands[1].reg << 16;
9686 inst.instruction |= inst.operands[0].reg;
9687 inst.instruction |= inst.operands[1].reg << 3;
9693 inst.instruction |= inst.operands[0].reg << r0off;
9702 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9703 inst.instruction |= (inst.operands[0].reg & 0x7);
9704 inst.instruction |= inst.operands[1].reg << 3;
9711 inst.instruction |= inst.operands[0].reg;
9712 inst.instruction |= inst.operands[1].reg << 3;
9719 inst.instruction |= inst.operands[0].reg;
9720 inst.instruction |= inst.operands[1].reg << 3;
9725 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9726 inst.instruction |= (inst.operands[0].reg & 0x7);
9727 inst.instruction |= inst.operands[1].reg << 3;
9737 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
9746 inst.instruction |= inst.operands[0].reg;
9747 inst.instruction |= inst.operands[1].reg << 3;
9760 constraint (inst.operands[0].reg > 7,
9762 inst.instruction |= inst.operands[0].reg << 8;
9785 inst.instruction |= inst.operands[0].reg << 8;
9808 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9824 inst.instruction |= inst.operands[0].reg << r0off;
9833 inst.instruction |= inst.operands[0].reg;
9834 inst.instruction |= inst.operands[1].reg << 3;
9843 inst.instruction |= inst.operands[0].reg << r0off;
9854 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9858 inst.instruction |= inst.operands[0].reg;
9859 inst.instruction |= inst.operands[1].reg << 3;
9888 inst.instruction |= inst.operands[0].reg << 8;
9920 inst.instruction |= inst.operands[1].reg << 16;
9927 inst.operands[2].reg = inst.operands[0].reg;
9933 inst.instruction |= inst.operands[0].reg << 8;
9934 inst.instruction |= inst.operands[1].reg << 16;
9935 inst.instruction |= inst.operands[2].reg << 0;
9941 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9945 inst.instruction |= inst.operands[0].reg;
9947 if (inst.operands[0].reg == inst.operands[1].reg)
9948 inst.instruction |= inst.operands[2].reg << 3;
9949 else if (inst.operands[0].reg == inst.operands[2].reg)
9950 inst.instruction |= inst.operands[1].reg << 3;
9959 inst.instruction |= inst.operands[0].reg << 12;
9960 inst.instruction |= inst.operands[1].reg << 8;
9961 inst.instruction |= inst.operands[2].reg << 16;
9962 inst.instruction |= inst.operands[3].reg;
9964 if (inst.operands[0].reg == inst.operands[1].reg)
10003 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
10011 inst.instruction |= inst.operands[0].reg << 8;
10012 inst.instruction |= inst.operands[1].reg << 16;
10017 inst.instruction |= inst.operands[0].reg;
10018 inst.instruction |= inst.operands[1].reg << 3;
10023 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
10028 inst.instruction |= inst.operands[0].reg;
10029 inst.instruction |= inst.operands[1].reg << 3;
10036 inst.instruction |= inst.operands[0].reg << 8;
10037 inst.instruction |= inst.operands[1].reg << 16;
10038 inst.instruction |= inst.operands[2].reg;
10100 inst.instruction |= inst.operands[0].reg << 8;
10101 inst.instruction |= inst.operands[1].reg << 16;
10107 inst.instruction |= inst.operands[0].reg << 8;
10108 inst.instruction |= inst.operands[1].reg;
10114 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10118 inst.instruction |= inst.operands[0].reg;
10119 inst.instruction |= inst.operands[1].reg << 3;
10124 inst.instruction |= inst.operands[0].reg << 8;
10125 inst.instruction |= inst.operands[1].reg << 16;
10126 inst.instruction |= inst.operands[1].reg;
10137 Rd = inst.operands[0].reg;
10139 ? inst.operands[1].reg /* Rd, Rs, foo */
10140 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10194 inst.operands[1].reg = inst.operands[0].reg;
10218 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
10223 && (inst.operands[1].reg != inst.operands[0].reg
10224 || inst.operands[2].reg > 7))
10234 inst.instruction |= inst.operands[0].reg << 8;
10235 inst.instruction |= inst.operands[1].reg << 16;
10236 inst.instruction |= inst.operands[2].reg;
10244 inst.instruction |= inst.operands[0].reg << 8;
10263 inst.instruction |= inst.operands[0].reg;
10264 inst.instruction |= inst.operands[2].reg << 3;
10276 inst.instruction |= inst.operands[0].reg;
10277 inst.instruction |= inst.operands[1].reg << 3;
10283 constraint (inst.operands[0].reg > 7
10284 || inst.operands[1].reg > 7, BAD_HIREG);
10289 constraint (inst.operands[2].reg > 7, BAD_HIREG);
10290 constraint (inst.operands[0].reg != inst.operands[1].reg,
10302 inst.instruction |= inst.operands[0].reg;
10303 inst.instruction |= inst.operands[2].reg << 3;
10316 inst.instruction |= inst.operands[0].reg;
10317 inst.instruction |= inst.operands[1].reg << 3;
10325 inst.instruction |= inst.operands[0].reg << 8;
10326 inst.instruction |= inst.operands[1].reg << 16;
10327 inst.instruction |= inst.operands[2].reg;
10345 inst.instruction |= inst.operands[0].reg << 8;
10347 inst.instruction |= inst.operands[2].reg << 16;
10368 inst.instruction |= inst.operands[0].reg << 8;
10370 inst.instruction |= inst.operands[2].reg << 16;
10382 inst.instruction |= inst.operands[0].reg << 8;
10383 inst.instruction |= inst.operands[1].reg << 12;
10384 inst.instruction |= inst.operands[2].reg << 16;
10392 inst.operands[2].reg = inst.operands[1].reg + 1;
10394 constraint (inst.operands[0].reg == inst.operands[1].reg
10395 || inst.operands[0].reg == inst.operands[2].reg
10396 || inst.operands[0].reg == inst.operands[3].reg
10397 || inst.operands[1].reg == inst.operands[2].reg,
10400 inst.instruction |= inst.operands[0].reg;
10401 inst.instruction |= inst.operands[1].reg << 12;
10402 inst.instruction |= inst.operands[2].reg << 8;
10403 inst.instruction |= inst.operands[3].reg << 16;
10409 inst.instruction |= inst.operands[0].reg << 8;
10410 inst.instruction |= inst.operands[1].reg << 16;
10411 inst.instruction |= inst.operands[2].reg;
10419 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10423 inst.instruction |= inst.operands[0].reg;
10424 inst.instruction |= inst.operands[1].reg << 3;
10430 inst.instruction |= inst.operands[0].reg << 8;
10431 inst.instruction |= inst.operands[1].reg;
10461 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
10467 inst.instruction |= inst.operands[0].reg << 8;
10469 inst.instruction |= inst.operands[2].reg << 16;
10490 inst.instruction |= inst.operands[0].reg << 8;
10492 inst.instruction |= inst.operands[2].reg << 16;
11533 inst.operands[0].reg = 13;
11604 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11605 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11606 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
11607 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
11608 inst.instruction |= LOW4 (inst.operands[2].reg);
11609 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
11628 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11629 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11630 inst.instruction |= LOW4 (inst.operands[1].reg);
11631 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11666 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11667 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11668 inst.instruction |= LOW4 (inst.operands[1].reg);
11669 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11702 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11704 tmp = inst.operands[2].reg;
11705 inst.operands[2].reg = inst.operands[1].reg;
11706 inst.operands[1].reg = tmp;
11732 tmp = inst.operands[2].reg;
11733 inst.operands[2].reg = inst.operands[1].reg;
11734 inst.operands[1].reg = tmp;
11748 tmp = inst.operands[2].reg;
11749 inst.operands[2].reg = inst.operands[1].reg;
11750 inst.operands[1].reg = tmp;
12032 inst.operands[1].reg : 0))
12069 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12070 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12234 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12235 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12236 inst.instruction |= LOW4 (inst.operands[1].reg);
12237 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12307 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
12308 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12309 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12310 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12311 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12435 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12436 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12437 inst.instruction |= LOW4 (inst.operands[1].reg);
12438 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12615 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12616 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12617 inst.instruction |= LOW4 (inst.operands[1].reg);
12618 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12718 constraint (inst.operands[0].reg != inst.operands[1].reg,
12801 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12802 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12803 inst.instruction |= LOW4 (inst.operands[1].reg);
12804 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12827 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12828 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12829 inst.instruction |= LOW4 (inst.operands[1].reg);
12830 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12861 immhi = inst.operands[1].reg;
12888 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12889 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12904 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12905 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12906 inst.instruction |= LOW4 (inst.operands[1].reg);
12907 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12929 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12930 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12931 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12932 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12933 inst.instruction |= LOW4 (inst.operands[2].reg);
12934 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13035 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13036 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13037 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13038 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13039 inst.instruction |= LOW4 (inst.operands[2].reg);
13040 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13073 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
13075 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
13081 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13082 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13105 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13106 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
13107 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
13137 (VFP single to ARM reg.)
13139 (ARM reg to VFP single.)
13187 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13188 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13189 inst.instruction |= LOW4 (inst.operands[1].reg);
13190 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13191 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13192 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13224 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
13225 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
13248 inst.instruction |= inst.operands[1].reg << 12;
13260 inst.instruction |= LOW4 (inst.operands[0].reg);
13261 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
13262 inst.instruction |= inst.operands[1].reg << 12;
13263 inst.instruction |= inst.operands[2].reg << 16;
13271 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
13272 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
13295 inst.instruction |= inst.operands[0].reg << 12;
13307 inst.instruction |= inst.operands[0].reg << 12;
13308 inst.instruction |= inst.operands[1].reg << 16;
13309 inst.instruction |= LOW4 (inst.operands[2].reg);
13310 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13342 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
13350 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
13497 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13498 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13499 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13500 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13501 inst.instruction |= LOW4 (inst.operands[2].reg);
13502 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13528 inst.instruction |= inst.operands[0].reg << 16;
13530 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13531 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
13849 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13850 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13851 inst.instruction |= inst.operands[1].reg << 16;
14263 the form alias .req reg, or a Neon .dn/.qn directive. */
17584 int reg = arm_reg_parse (®name, REG_TYPE_RN);
17586 if (reg == FAIL)
17589 return reg;