gas/config/tc-arm.c

3217   valueT op;
3258 	  op = 0x8000 | ((range >> 4) & 0xfff);
3259 	  add_unwind_opcode (op, 2);
3265 	    op = 0xa8; /* Pop r14.	*/
3267 	    op = 0xa0; /* Do not pop r14.  */
3268 	  op |= (n - 1);
3269 	  add_unwind_opcode (op, 1);
3276       op = 0xb100 | (range & 0xf);
3277       add_unwind_opcode (op, 2);
3296   valueT op;
3325       op = 0xb4 | (num_regs - 1);
3326       add_unwind_opcode (op, 1);
3331       op = 0xc800 | (reg << 4) | (num_regs - 1);
3332       add_unwind_opcode (op, 2);
3345   valueT op;
3371       op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3372       add_unwind_opcode (op, 2);
3380       op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3381       add_unwind_opcode (op, 2);
3395   valueT op;
3410       op = 0xb8 | (count - 1);
3411       add_unwind_opcode (op, 1);
3416       op = 0xb300 | (reg << 4) | (count - 1);
3417       add_unwind_opcode (op, 2);
3432   valueT op;
3510 	      op = 0xffff << (reg - 1);
3512 		  && ((mask & op) == (1u << (reg - 1))))
3514 		  op = (1 << (reg + i + 1)) - 1;
3515 		  op &= ~((1 << reg) - 1);
3516 		  mask |= op;
3539 		  op = 0xc0 | (hi_reg - 10);
3540 		  add_unwind_opcode (op, 1);
3545 		  op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3546 		  add_unwind_opcode (op, 2);
3564   valueT op;
3618   op = 0xc700 | mask;
3619   add_unwind_opcode (op, 2);
3689   valueT op;
3721   op = 0x90 | reg;
3722   add_unwind_opcode (op, 1);
3810   unsigned char op[16];
3846       op[count++] = exp.X_add_number;
3857     add_unwind_opcode (op[count], 1);
3902      pseudo-op name without dot
3903      function to call to execute this pseudo-op
4612       /* else a load-constant pseudo op, no special treatment needed here */
6578 /* This is a pseudo-op of the form "adr rd, label" to be converted
6593 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7006   /* If op 1 were present and equal to PC, this function wouldn't
7587   /* If op 2 were present and equal to PC, this function wouldn't
11840    the instruction. *OP is passed as the initial value of the op field, and
11848 			 unsigned *immbits, int *op, int size,
11858       if (size != 32 || *op == 1)
11869 	  if (*op == 1)
11873 	  *op = 1;
11940       if (*op == 1)
12029 	  /* .i64 is a pseudo-op, so the immediate must be a repeating
12193      V<op> A,B     (A is operand 0, B is operand 2)
12195      V<op> A,B,A
12197      V<op> A,B,B
12564      VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12851   int op, cmode, float_p;
12857   op = (inst.instruction & (1 << 5)) != 0;
12868   if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
12876       op = !op;
12878 					    &op, et.size, et.type)) == FAIL)
12886   inst.instruction |= op << 5;
12944   /* FIXME: Type checking for lengthening op.  */
13053   unsigned op = (inst.instruction >> 7) & 3;
13057   unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14794 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14795   { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14807 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14808   { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14810 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14811   { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14824 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te)	\
14826     0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14828 #define TxCM(m1, m2, op, top, nops, ops, ae, te)	\
14829   TxCM_(m1,   , m2, op, top, nops, ops, ae, te),	\
14830   TxCM_(m1, eq, m2, op, top, nops, ops, ae, te),	\
14831   TxCM_(m1, ne, m2, op, top, nops, ops, ae, te),	\
14832   TxCM_(m1, cs, m2, op, top, nops, ops, ae, te),	\
14833   TxCM_(m1, hs, m2, op, top, nops, ops, ae, te),	\
14834   TxCM_(m1, cc, m2, op, top, nops, ops, ae, te),	\
14835   TxCM_(m1, ul, m2, op, top, nops, ops, ae, te),	\
14836   TxCM_(m1, lo, m2, op, top, nops, ops, ae, te),	\
14837   TxCM_(m1, mi, m2, op, top, nops, ops, ae, te),	\
14838   TxCM_(m1, pl, m2, op, top, nops, ops, ae, te),	\
14839   TxCM_(m1, vs, m2, op, top, nops, ops, ae, te),	\
14840   TxCM_(m1, vc, m2, op, top, nops, ops, ae, te),	\
14841   TxCM_(m1, hi, m2, op, top, nops, ops, ae, te),	\
14842   TxCM_(m1, ls, m2, op, top, nops, ops, ae, te),	\
14843   TxCM_(m1, ge, m2, op, top, nops, ops, ae, te),	\
14844   TxCM_(m1, lt, m2, op, top, nops, ops, ae, te),	\
14845   TxCM_(m1, gt, m2, op, top, nops, ops, ae, te),	\
14846   TxCM_(m1, le, m2, op, top, nops, ops, ae, te),	\
14847   TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14857 #define TUE(mnem, op, top, nops, ops, ae, te)				\
14858   { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14863 #define TUF(mnem, op, top, nops, ops, ae, te)				\
14864   { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14868 #define CE(mnem,  op, nops, ops, ae)	\
14869   { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14871 #define C3(mnem, op, nops, ops, ae)	\
14872   { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14876 #define CL(mnem, op, nops, ops, ae)	\
14878     0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14881 #define cCE(mnem,  op, nops, ops, ae)	\
14882   { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14887 #define cCL(mnem, op, nops, ops, ae)	\
14889     0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14893 #define C3E(mnem, op, nops, ops, ae) \
14895     0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14897 #define xCM_(m1, m2, m3, op, nops, ops, ae)	\
14900     0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14902 #define CM(m1, m2, op, nops, ops, ae)	\
14903   xCM_(m1,   , m2, op, nops, ops, ae),	\
14904   xCM_(m1, eq, m2, op, nops, ops, ae),	\
14905   xCM_(m1, ne, m2, op, nops, ops, ae),	\
14906   xCM_(m1, cs, m2, op, nops, ops, ae),	\
14907   xCM_(m1, hs, m2, op, nops, ops, ae),	\
14908   xCM_(m1, cc, m2, op, nops, ops, ae),	\
14909   xCM_(m1, ul, m2, op, nops, ops, ae),	\
14910   xCM_(m1, lo, m2, op, nops, ops, ae),	\
14911   xCM_(m1, mi, m2, op, nops, ops, ae),	\
14912   xCM_(m1, pl, m2, op, nops, ops, ae),	\
14913   xCM_(m1, vs, m2, op, nops, ops, ae),	\
14914   xCM_(m1, vc, m2, op, nops, ops, ae),	\
14915   xCM_(m1, hi, m2, op, nops, ops, ae),	\
14916   xCM_(m1, ls, m2, op, nops, ops, ae),	\
14917   xCM_(m1, ge, m2, op, nops, ops, ae),	\
14918   xCM_(m1, lt, m2, op, nops, ops, ae),	\
14919   xCM_(m1, gt, m2, op, nops, ops, ae),	\
14920   xCM_(m1, le, m2, op, nops, ops, ae),	\
14921   xCM_(m1, al, m2, op, nops, ops, ae)
14923 #define UE(mnem, op, nops, ops, ae)	\
14924   { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14926 #define UF(mnem, op, nops, ops, ae)	\
14927   { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14932 #define NUF(mnem, op, nops, ops, enc)					\
14933   { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op,		\
14938 #define nUF(mnem, op, nops, ops, enc)					\
14939   { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op,	\
14944 #define NCE_tag(mnem, op, nops, ops, enc, tag)				\
14945   { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT,		\
14948 #define NCE(mnem, op, nops, ops, enc)					\
14949   NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14951 #define NCEF(mnem, op, nops, ops, enc)					\
14952   NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14955 #define nCE_tag(mnem, op, nops, ops, enc, tag)				\
14956   { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op,		\
14959 #define nCE(mnem, op, nops, ops, enc)					\
14960   nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14962 #define nCEF(mnem, op, nops, ops, enc)					\
14963   nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14968 #define UT(mnem,  op, nops, ops, te) TUE(mnem,  0, op, nops, ops, 0, te)
16929   int op;
16932   op = bfd_get_16(sec->owner, buf);
16933   if ((op & 0xf) == ((op >> 4) & 0xf))
17220    be passed as op[0] << 8 | op[1].  The list of opcodes is built in reverse
17224 add_unwind_opcode (valueT op, int length)
17244       unwind.opcodes[unwind.opcode_count] = op & 0xff;
17245       op >>= 8;
17255   valueT op;
17290       op = (offset - 0x104) >> 2;
17291       add_unwind_opcode (op, 1);
17296       op = (offset - 4) >> 2;
17297       add_unwind_opcode (op, 1);
17307       op = ((offset - 4) >> 2) | 0x40;
17308       add_unwind_opcode (op, 1);
17316   valueT op;
17325       op = 0x90 | unwind.fp_reg;
17326       add_unwind_opcode (op, 1);
17787   int op, new_inst;
17793   op = (*instruction >> DATA_OP_SHIFT) & 0xf;
17794   switch (op)
17866   int op, new_inst;
17874   op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
17875   switch (op)
17955 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
17957   if (op == O_subtract