Lines Matching defs:immediate
339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
739 /* Prefix characters that indicate the start of an immediate
787 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
807 inst.error = _("immediate expression requires a # prefix");
972 /* Generic immediate-value read function for use in directives.
3973 /* Generic immediate-value read function for use in insn parsing.
3974 STR points to the beginning of the immediate (the leading #);
3976 issue an error. PREFIX_OPT is true if the immediate prefix is
3993 inst.error = _("immediate value out of range");
4001 /* Less-generic immediate-value read function with the possibility of loading a
4002 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4053 /* Returns the pseudo-register number of an FPA immediate constant,
4140 inst.error = _("invalid FPA immediate expression");
4234 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4235 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4236 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4237 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4332 #<immediate>
4333 #<immediate>, <rotate>
4338 multiple of 2 between 0 and 30. Validation of immediate operands
4510 #<immediate>
4511 #<immediate>, <rotate>
4589 =immediate .isreg=0 .reloc.exp=immediate
4791 /* We might be using the immediate for alignment already. If we
4873 inst.error = _("immediate value out of range");
5405 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5406 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
5407 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
5413 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */
5414 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
5415 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5417 OP_I0, /* immediate zero */
5418 OP_I7, /* immediate value 0 .. 7 */
5432 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
5444 OP_EXPi, /* same, with optional immediate prefix */
5460 OP_RF_IF, /* FPA register or immediate */
5465 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
5478 OP_oSHll, /* LSL immediate */
5479 OP_oSHar, /* ASR immediate */
5480 OP_oSHllar, /* LSL or ASR immediate */
5644 /* There's a possibility of getting a 64-bit immediate here, so
5648 inst.error = _("immediate value is out of range");
5714 /* There's a possibility of getting a 64-bit immediate here, so
5718 inst.error = _("immediate value is out of range");
5833 /* Register or immediate */
6020 do not signal immediate failures for the register constraints;
6120 /* If VAL can be encoded in the immediate field of an ARM instruction,
6135 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6219 /* Encode a <shift> in an ARM-format instruction. The immediate,
6316 else /* immediate offset in inst.reloc */
6345 else /* immediate offset in inst.reloc */
6680 BKPT <16 bit unsigned immediate>
7106 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8078 _("immediate operand requires iWMMXt2"));
8154 /* Maverick shift immediate instructions.
8166 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8167 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8519 _("immediate value out of range"));
8691 /* For an immediate, we always generate a 32-bit opcode;
8774 /* For an immediate, we always generate a 32-bit opcode;
9001 _("immediate value out of range"));
9661 /* Some mov with immediate shift have narrow variants.
9761 _("only lo regs allowed with immediate"));
9819 /* For an immediate, we always generate a 32-bit opcode;
9902 _("Thumb encoding does not support an immediate here"));
10545 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11755 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
11763 immediate |= immediate << 8;
11769 if (immediate == (immediate & 0x000000ff))
11771 *immbits = immediate;
11774 else if (immediate == (immediate & 0x0000ff00))
11776 *immbits = immediate >> 8;
11779 else if (immediate == (immediate & 0x00ff0000))
11781 *immbits = immediate >> 16;
11784 else if (immediate == (immediate & 0xff000000))
11786 *immbits = immediate >> 24;
11789 if ((immediate & 0xffff) != (immediate >> 16))
11791 immediate &= 0xffff;
11794 if (immediate == (immediate & 0x000000ff))
11796 *immbits = immediate;
11799 else if (immediate == (immediate & 0x0000ff00))
11801 *immbits = immediate >> 8;
11806 first_error (_("immediate value out of range"));
11822 /* For immediate of above form, return 0bABCD. */
11843 MVN). If the immediate looks like a repeated parttern then also
11939 /* Don't allow MVN with 8-bit immediate. */
11949 /* Write immediate bits [7:0] to the following locations:
12029 /* .i64 is a pseudo-op, so the immediate must be a repeating
12454 _("immediate out of range for insert"));
12466 _("immediate out of range for insert"));
12478 _("immediate out of range for shift"));
12483 /* The rest of the bits are the same as other immediate shifts. */
12520 /* This gets the bounds check, size encoding and immediate bits calculation
12535 _("immediate out of range"));
12547 /* This gets the bounds check, size encoding and immediate bits calculation
12562 _("immediate out of range"));
12584 /* This gets the bounds check, size encoding and immediate bits calculation
12588 /* If immediate is zero then we are a pseudo-instruction for
12599 _("immediate out of range for narrowing operation"));
12649 /* The instruction versions which take an immediate take one register
12692 /* Conversions with immediate bitshift. */
12792 /* Fixed-point conversion with #0 immediate is encoded as an
12854 _("operand size must be specified for immediate VMOV"));
12864 _("immediate has bits set outside the operand size"));
12873 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12880 first_error (_("immediate out of range"));
13135 (VFP float immediate load.)
13326 first_error (_("immediate out of range"));
13380 _("immediate out of range for shift"));
13609 /* Bits [4:6] of the immediate in a list specifier encode register stride
16036 /* If not immediate, fall back to neon_dyadic_i64_su.
16068 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
16134 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16137 /* Right shift immediate, saturating & narrowing, with rounding variants.
16149 /* CVT with optional immediate for fixed-point variant. */
16849 /* Return the size of a relaxable immediate operand instruction.
16850 SHIFT and SIZE specify the form of the allowable immediate. */
16924 /* Return the size of a relaxable add/sub immediate instruction. */
17725 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17726 computed as two separate immediate values, added together. We
17773 negative immediate constant by altering the instruction. A bit of
18022 _("undefined symbol %s used as an immediate value"),
18111 _("bad immediate value for offset (%ld)"),
18135 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18149 _("bad immediate value for offset (%ld)"), (long) value);
18159 load/store instruction with immediate offset:
18306 _("undefined symbol %s used as an immediate value"),
18330 /* 12 bit immediate for addw/subw. */
18738 the following immediate relocations:
18763 _("invalid Hi register with immediate"));
18772 _("immediate value out of range"));
18779 _("invalid immediate for stack address calculation"));
18787 _("invalid immediate for address calculation (value = 0x%08lX)"),
18797 _("immediate value out of range"));
18805 _("immediate value out of range"));
18817 _("invalid immediate: %ld is too large"),