Lines Matching refs:CSR_SETBIT_1
248 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
249 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
255 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
373 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
409 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
440 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
453 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
468 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
478 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
495 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
498 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
507 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
2060 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES);
2064 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
2066 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
2071 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
2074 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
2235 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2240 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2242 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2880 CSR_SETBIT_1(sc, VGE_DIAGCTL,