Lines Matching defs:mphy_ctrl
4120 u32 mphy_ctrl = 0;
4132 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4133 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4138 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4139 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4148 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4151 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4182 u32 mphy_ctrl = 0;
4194 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4195 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4200 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4201 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4211 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4213 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4214 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4216 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4244 u32 mphy_ctrl = 0;
4248 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4249 if (mphy_ctrl & E1000_MPHY_BUSY) {