Lines Matching defs:to
24 along with GAS; see the file COPYING. If not, write to the Free
66 /* The number of bytes pushed to the stack. */
73 hold the reg+offset to use when restoring sp from a frame pointer. */
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
105 /* Types of processor to assemble for. */
129 /* For backwards compatibility, default to FPA. */
148 options have been read we re-process these values to set the real
227 /* Must be long enough to hold any of the names in arm_cpus. */
260 that formerly had them in the middle, continue to accept them
311 /* "uncond_value" is set to the value in place of the conditional field in
316 /* Set to the opcode if the instruction needs relaxation.
337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
338 instructions. This allows us to disambiguate ARM <-> vector insns. */
348 unsigned shifted : 1; /* Shift applied to operation. */
362 /* Number of littlenums required to hold an extended precision number. */
468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
506 /* Some well known registers that we refer to directly elsewhere. */
517 /* Basic string to match. */
520 /* Parameters to instruction. */
536 /* Function to call to encode instruction in ARM format. */
539 /* Function to call to encode instruction in Thumb format. */
543 /* Defines for various bits that we will want to toggle. */
565 /* Codes to distinguish the arithmetic instructions. */
652 #define BAD_ARGS _("bad arguments to instruction")
674 /* Stuff needed to resolve the label ambiguity
703 /* Pointer to a linked list of literal pools. */
719 a line. If the line seems to have the form '# 123 filename'
729 /* Chars that can be used to separate mant
782 /* Third argument to my_get_expression. */
885 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
923 return _("bad call to MD_ATOF()");
973 Accepts anything that 'expression' can fold to a constant.
1001 /* Generic register parser. CCP points to what should be the
1088 /* Do not allow a scalar (reg+index) to parse as a register. */
1113 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1355 in the struct pointed to by VECTYPE (if non-NULL).
1370 /* Do not allow a scalar (reg+index) to parse as a register. */
1389 have enough information to be able to do a good job bounds-checking. So, we
1558 Otherwise return the number of registers, and set PBASE to the first
1561 - Q registers can be used to specify pairs of D registers
1971 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2004 first_error (_("attempt to redefine typed alias"));
2019 If we find one, or if it looks sufficiently like one that we want to
2030 collapsed to single spaces. */
2046 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2047 the desired alias name, and p points to its end. If not, then
2273 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2323 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2339 There is nothing else to do. */
2408 /* The compiler may generate BL instructions to local labels because
2409 it needs to perform a branch to a far away location. These labels
2411 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2421 as_warn ("Failed to find real start of function: %s\n", name);
2440 /* No need to force the alignment, since we will have been
2496 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2506 to compile interworking support functions even if the
2523 We need to know this for the interworking support. */
2534 We cannot just call that code as we need to get at the symbol that
2563 /* XXX - this should not happen to .thumb_set. */
2572 outside the normal fragment chain to record the file and line info
2608 /* XXX Now we come to the Thumb specific bit of code. */
2679 /* Only make a frag if we HAVE to. */
2753 /* Add it to the list. */
2770 structure to the relevent literal pool. */
2802 /* Do we need to create a new entry? */
2822 /* Can't use symbol_new here, so have to create a symbol and then at
2852 /* Link to end of symbol chain. */
2890 Only make a frag if we have to. */
2909 /* First output the expression in the instruction to the pool. */
2989 XXX Surely there is a cleaner way to do this. */
3124 /* Indicate dependency on EHABI-defined personality routines to the
3246 /* See if we can use the short opcodes. These pop a block of up to 8
3298 /* Get Number of registers to transfer. */
3476 /* Generate any deferred opcodes because we're going to be looking at
3486 /* Attempt to combine with a previous opcode. We do this because gcc
3487 likes to output separate unwind directives for a single block of
3524 /* We want to generate opcodes in the order the registers have been
3532 /* We found an unsaved reg. Generate opcodes to save the
3609 /* Generate any deferred opcodes because we're going to be looking at
3720 /* Generate opcode to restore the value. */
3901 has to support. The fields are:
3903 function to call to execute this pseudo-op
3904 Integer arg to pass to the function. */
3974 STR points to the beginning of the immediate (the leading #);
4017 O_constant. We have to be careful not to break compilation for
4065 /* First try and match exact strings, this is to guarantee
4230 /* Third argument to parse_shift. */
4247 Note that ASL is assimilated to LSL in the instruction encoding, and
4248 RRX to ROR #0 (which cannot be written as such). */
4339 is deferred to md_apply_fix. */
4390 /* Convert to decoded value. md_apply_fix will put it back. */
4404 Along with this textual name are the relocation codes to be used if
4480 /* Given the address of a pointer pointing to the textual name of a group
4481 relocation as may appear in assembler source, attempt to find its details
4482 in group_reloc_table. The pointer will be updated to the character after
4484 otherwise. On success, *entry will be updated to point at the relevant
4526 If we don't, punt the whole lot to parse_shifter_operand. */
4538 /* Try to parse a group relocation. Anything else is an error. */
4545 /* We now have the group relocation table entry corresponding to
4564 to inst.operands[i] and/or inst.reloc.
4573 These three may have a trailing ! which causes .writeback to be set also.
4592 It is the caller's responsibility to check for addressing modes not
4593 supported by the instruction, and to set inst.reloc.type. */
4606 /* bare address - translate to PC-relative offset */
4648 code before we get to see it here. This may be subject to
4682 /* Try to parse a group relocation. Anything else is an
4690 /* We now have the group relocation table entry corresponding to
4867 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4930 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5072 /* Parse the operands of a table branch instruction. Similar to a memory
5129 Up to four operands may be read; this function handles setting the
5554 /* Remember where we are in case we need to backtrack. */
5607 /* WARNING: We can expand to two operands here. This has the potential
5608 to totally confuse the backtracking mechanism! It will be OK at
5609 least as long as we don't try to use optional args as well,
5621 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5761 to find it first and zap it. */
6004 this allows a syntax error to take precedence. */
6399 it can, convert inst.instruction to that move instruction and
6400 return 1; if it can't, convert inst.instruction to a literal-pool
6401 load and return 0. If this is not a valid thing to do in the
6561 /* This is a pseudo-op of the form "adr rd, label" to be converted
6570 out to be negative. */
6576 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6587 out to be negative. */
6665 and it is an error if the caller tried to override that. */
6670 /* Top 12 of 16 bits to bits 19:8. */
6673 /* Bottom 4 of 16 bits to bits 3:0. */
6734 It is not illegal to do "blx pc", just useless. */
6765 /* ARM v5TEJ. Jump to Jazelle code. */
6930 register and the first register written; we have to diagnose
6962 It is very difficult to distinguish between these two cases
6966 message and leave it up to the programmer to discover the
6988 /* If op 1 were present and equal to PC, this function wouldn't
7069 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7173 /* Or in the registers to use */
7195 /* Or in the registers to use */
7263 /* rdhi, rdlo and rm must all be different prior to ARMv6. */
7284 Condition defaults to COND_ALWAYS.
7569 /* If op 2 were present and equal to PC, this function wouldn't
7584 extends it to 32-bits, and adds the result to a value in another
7588 Condition defaults to COND_ALWAYS.
7603 Condition defaults to COND_ALWAYS.
7896 unstacking, so we have to emulate these by setting appropriate
8195 /* Encoding functions relevant only to Thumb. */
8464 /* Attempt to use a narrow opcode, with relaxation if
8598 /* We now have Rd, Rs, and Rn set to registers. */
8627 /* Defer to section relaxation. */
8737 commutative, so we can allow either of them to be different from
8899 ??? How to take advantage of the additional two bits of displacement
8997 the (interfacearm) attribute. We look for the Thumb entry point to that
8998 function and change the branch to refer to that function instead. */
9013 should cause the alignment to be checked once it is known. This is
10074 inst.error = _("invalid register list to push/pop instruction");
10491 /* Map overloaded Neon opcodes to their respective encodings. */
10589 This table is used to generate various data:
10590 - enumerations of the form NS_DDR to be used as arguments to
10593 - a table used to drive neon_select_shape.
10720 set, various other bits can be set as well in order to modify the meaning of
10750 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */
10751 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10752 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */
10753 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */
10754 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10768 /* Pass this as the first type argument to neon_check_type to ignore types
10775 function of operand parsing, so this function doesn't need to be called.
10879 /* Allow modification to be made to types which are constrained to be
10991 /* Convert compact Neon bitmask type representation to a type and size. Only
11160 /* Decay more-specific signed & unsigned types to sign-insensitive
11166 /* If only untyped args are allowed, decay any more specific types to
11302 /* Check operand types to see if this is a VFP instruction, and if so call
11393 insns belong to Neon, and are handled elsewhere. */
11542 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11549 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11813 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11821 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11823 may be set to a different value depending on the constant (i.e.
11931 /* Write immediate bits [7:0] to the following locations:
12016 /* Set immbits to an invalid constant. */
12097 operand parsing so we don't need to do anything extra here. */
12104 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12115 /* Call this function if an instruction which may have belonged to the VFP or
12116 Neon instruction sets, but turned out to be a Neon instruction (due to the
12117 operand types involved, etc.). We have to check and/or fix-up a couple of
12120 - Make sure the user hasn't attempted to make a Neon instruction
12130 changed to inst.uncond_value. This is necessary because instructions shared
12168 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12174 result to be:
12176 to mean:
12322 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12462 In this case, signed types have OP (bit 8) set to 0.
12463 Unsigned types have OP set to 1. */
12632 argument, which is extended to the width of the full register. Thus the
12634 here by making the size equal to the key (wider, in this case) operand. */
12855 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12979 so force the operand type to integer. */
13037 extract it here to check the elements to be reversed are smaller.
13078 /* Duplicate ARM register to lanes of vector. */
13105 (ARM register to scalar.)
13107 (Two ARM registers to vector.)
13109 (Scalar to ARM register.)
13111 (Vector to two ARM registers.)
13119 (VFP single to ARM reg.)
13121 (ARM reg to VFP single.)
13123 (Two ARM regs to two VFP singles.)
13125 (Two VFP singles to two ARM regs.)
13136 can specify a type where it doesn't make sense to, and is ignored).
13320 (one of which is a list), but we have parsed four. Do some fiddling to
13608 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13733 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13861 /* We need to be able to fix up arbitrary expressions in some statements.
13893 /* Mark whether the fix is to a THUMB instruction, or an ARM
13902 char * to;
13906 /* The size of the instruction is unknown, so tie the debug info to the
13925 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
13927 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
13930 /* Write a 32-bit thumb instruction to buf. */
13941 char * to = NULL;
13955 to = frag_more (inst.size);
13960 put_thumb32_insn (to, inst.instruction);
13965 md_number_to_chars (to, inst.instruction, INSN_SIZE);
13966 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
13969 md_number_to_chars (to, inst.instruction, inst.size);
13972 fix_new_arm (frag_now, to - frag_now->fr_literal,
14005 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
14014 opcode from the mnemonic the user wrote. STR points to the
14019 expressed with a _conditional affix_ to the mnemonic. If we were
14020 to encode each conditional variant as a literal string in the opcode
14024 'most' is upgraded to 'all'. However, in the divided syntax, some
14033 If we find a match, go to step U.
14038 find a match, go to step CE.
14044 to step CM.
14050 unusual place. If it is, the tag tells us where to find the
14055 CE. Examine the tag field to make sure this is an instruction that
14060 CM. Examine the tag field to make sure this is an instruction that
14062 If it is not, fail. Otherwise, undo the edits to the current
14077 /* Scan up to the end of the mnemonic, which must end in white space,
14333 /* Something has gone badly wrong if we try to relax a fixed size
14383 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14409 /* Note - do not allow local symbols (.Lxxx) to be labeled
14433 to have the bottom bit set, which in turn would mean that the
14444 interworking between Arm and Thumb functions to work
14796 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
15019 /* These may simplify to neg. */
15030 /* V1 instructions with no Thumb analogue prior to V6T2. */
15943 /* Instructions which may belong to either the Neon or VFP instruction sets.
15949 /* These mnemonics are unique to VFP. */
16010 /* If not immediate, fall back to neon_dyadic_i64_su.
16043 back to neon_dyadic_if_su. */
16135 /* If not scalar, fall back to neon_dyadic_long.
16603 for use in the a.out file, and stores them in the array pointed to by buf.
16832 /* ??? Should be able to do better than this. */
16839 /* Force misaligned offsets to 32-bit variant. */
16861 /* If frag has yet to be reached on this pass, assume it will
16881 /* Assume worst case for symbols not known to be in the same section. */
16889 /* Force misaligned targets to 32-bit variant. */
16924 /* Assume worst case for symbols not known to be in the same section. */
17020 /* Round up a section size to the appropriate boundary. */
17029 /* For a.out, force the section size to be aligned. If we don't do
17032 easier to fix it here since that is how the other a.out targets
17106 /* Called from md_do_align. Used to create an alignment
17115 to support alignments greater than 32 bytes. */
17139 /* When we change sections we need to issue a new mapping symbol. */
17147 /* Link an unlinked unwind index table section to the .text section. */
17176 /* Code to deal with unwinding tables. */
17193 /* Add an opcode to this list for this function. Two-byte opcodes should
17224 /* Add unwind opcodes to adjust the stack pointer. */
17233 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17483 /* Set the first byte to the number of additional words. */
17553 /* Convert REGNAME to a DWARF-2 register number. */
17582 relative to. For ARM, PC-relative fixups applied to instructions
17583 are generally relative to the location of the fixup plus 8 bytes.
17584 Thumb branches are offset by 4, and Thumb loads relative to PC
17592 /* If this is pc-relative and we are going to emit a relocation
17593 then we just want to put out any pipeline compensation that the linker
17594 will need. Otherwise we want to use the calculated base.
17596 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17609 bottom two bits of the PC are forced to zero for the
17633 loader expects the relocation not to take this into account. */
17656 /* ARM mode loads relative to PC are also offset by +8. Unlike
17658 to take this into account. */
17673 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17674 Otherwise we have no need to default values of symbols. */
17699 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17923 /* We usually want to set the low bit on the address of thumb function
17925 Generic code tries to fold the difference of two symbols to
17964 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17982 /* This will need to go in the object file. */
18032 /* No ? OK - try using two ADD instructions to generate
18047 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18055 do not want to do it again. */
18082 _("invalid literal constant: pool needs to be closer"));
18107 _("invalid literal constant: pool needs to be closer"));
18389 /* We are going to store value (shifted right by two) in the
18420 /* Attempts to use CBZ to branch to the next instruction
18424 FIXME: It may be better to remove the instruction completely and
18506 to a word boundary. This follows the semantics of the instruction
18652 forced to zero for these loads; md_pcrel_from has already
18703 "Unable to process relocation for thumb opcode: %lx",
18733 Adjusting SP, and using PC or SP to get an address. */
18825 /* REL format relocations are limited to a 16-bit addend. */
18889 Otherwise use a SUB. Take care not to destroy the S bit. */
19036 /* Translate internal representation of relocation info to BFD target
19272 vtable entry to be used in the relocation's section offset. */
19326 the (interfacearm) attribute. We look for the Thumb entry point to that
19327 function and change the branch to refer to that function instead. */
19373 so that the linker can use this information to generate interworking
19379 There is one other problem that ought to be addressed here, but
19381 than a function) and then later jumping to that address. Such
19382 addresses also ought to have their bottom bit set (assuming that
19404 /* Don't allow symbols to be discarded on GOT related relocs. */
19463 /* A good place to do this, although this was probably not intended
19464 for this kind of use. We need to dump the literal pool before
19465 references are made to a null symbol pointer. */
19629 as_bad (_("use of old and new-style options to set CPU type"));
19639 as_bad (_("use of old and new-style options to set FPU type"));
19729 /* No additional flags to set. */
19738 /* We have run out flags in the COFF header to encode the
19805 The new options try to make the interface as compatible as
19888 char *option; /* Option name to match. */
19890 int *var; /* Variable to change. */
19891 int value; /* What to change it to. */
19919 char *option; /* Option name to match. */
19920 const arm_feature_set **var; /* Variable to change. */
19921 const arm_feature_set value; /* What to change it to. */
19927 /* DON'T add any new processors to this list -- we want the whole list
19928 to go away... Add them to the processors table instead. */
20008 /* Architecture variants -- don't add any more to this list either. */
20028 /* Floating point variants -- don't add any more to this list either. */
20045 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20098 /* For V5 or later processors we default to using VFP; but the user
20265 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20277 char * option; /* Substring to match. */
20279 int (* func) (char * subopt); /* Function to decode sub-option. */
20550 /* These options are expected to have an argument. */
20609 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20642 /*Allow the user to override the reported architecture. */