gas/config/tc-arm.c

339     unsigned regisimm   : 1;  /* 64-bit immediate, reg forms high 32 bits.  */
406 /* The individual PSR flag bits.  */
543 /* Defines for various bits that we will want to toggle.  */
1192    (particularly in the Neon bits), but usually the earliest error which is set
1766    The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
3254       /* See if there are any other bits set.  */
4031       /* Bignums have their least significant bits in
4032          generic_bignum[0]. Make sure we put 32 bits in imm and
4033          32 bits in reg,  in a (hopefully) portable way.  */
4198       /* Our FP word must be 32 bits (single-precision FP).  */
4775                  are, OR the register number into the low-order bits.  */
6670   /* Top 12 of 16 bits to bits 19:8.  */
6673   /* Bottom 4 of 16 bits to bits 3:0.  */
6726    Also, the <target_addr> can be 25 bits, hence has its own reloc.  */
7276       /* Architectural NOP hints are CPSR sets with no bits selected.  */
7426    preserving the other bits.
7584    extends it to 32-bits, and adds the result to a value in another
7585    register.  You can specify a rotation by 0, 8, 16, or 24 bits
7897 	 bits and offsets.  */
8148   /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8149      Bits 5-7 of the insn should have bits 4-6 of the immediate.
8567 	  /* If we get here, it can't be done in 16 bits.  */
8707 	  /* If we get here, it can't be done in 16 bits.  */
8799 	  /* If we get here, it can't be done in 16 bits.  */
8899    ??? How to take advantage of the additional two bits of displacement
10720    set, various other bits can be set as well in order to modify the meaning of
10880      based on the key element, based on bits set alongside N_EQK.  */
10900 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11248    Neon-style VFP syntax.  This avoids duplication of bits of the insns table,
11541 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11580   SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11792 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11821 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11931 /* Write immediate bits [7:0] to the following locations:
11946 /* Invert low-order SIZE bits of XHI:XLO.  */
12125    Which of these operations take place depends on bits from enum
12247    scalars, which are encoded in 5 bits, M : Rm.
12465   /* The rest of the bits are the same as other immediate shifts.  */
12502   /* This gets the bounds check, size encoding and immediate bits calculation
12529   /* This gets the bounds check, size encoding and immediate bits calculation
12566   /* This gets the bounds check, size encoding and immediate bits calculation
12846               _("immediate has bits set outside the operand size"));
12853       /* Invert relevant bits only.  */
13130    All the encoded bits are hardcoded by this function.
13493   /* P, U and L bits are part of bitmask.  */
13551   /* The bits in this table go:
13592      (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13593      VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13807 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13808    apart from bits [11:4].  */
14340 	 set those bits when Thumb-2 32-bit instructions are seen.  ie.
14601      truly all possible PSR bits.  */
14904    The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14966     for setting PSR flag bits.  They are obsolete in V6 and do not
15800      does not set any bits.  */
16600 /* MD interface: bits in the object file.  */
16918 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
16934   limit = 1 << bits;
17609 	 bottom two bits of the PC are forced to zero for the
17964   /* On a 64-bit host, silently truncate 'value' to 32 bits for
18145 	 Uppercase letters indicate bits that are already encoded at
18148 	 (bits 8..11) is present, and bit 23 is zero, even if this is
18647 	 top 4 bits.  */
18896          /* Place the encoded addend into the first 12 bits of the
18919              encoded in 12 bits.  */
18922 	  	          _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18935           /* Place the absolute value of the addend into the first 12 bits
18958              encoded in 8 bits.  */
18961 	  	          _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18974           /* Place the first four bits of the absolute value of the addend
18975              into the first 4 bits of the instruction, and the remaining
18976              four into bits 8 .. 11.  */
18998              four and, when divided by four, fits in 8 bits.  */
19020              bits of the instruction.  */