Lines Matching refs:TLB
63 TLB, /* TLB */
64 STLB, /* Shared second-level unified TLB */
72 INST, /* Instruction TLB */
73 DATA, /* Data TLB */
74 DATA0, /* Data TLB, 1st level */
75 DATA1, /* Data TLB, 2nd level */
83 SMALL, /* Small page TLB */
84 LARGE, /* Large page TLB */
85 BOTH /* Small and Large page TLB */
91 uint8_t level; /* level of cache/TLB hierachy */
93 uint16_t size; /* cachesize or TLB pagesize */
94 uint16_t entries; /* number of TLB entries or linesize */
111 { 0x01, TLB, INST, 4, SMALL, 32 },
112 { 0x02, TLB, INST, FULLY, LARGE, 2 },
113 { 0x03, TLB, DATA, 4, SMALL, 64 },
114 { 0x04, TLB, DATA, 4, LARGE, 8 },
115 { 0x05, TLB, DATA1, 4, LARGE, 32 },
120 { 0x0B, TLB, INST, 4, LARGE, 4 },
146 { 0x4F, TLB, INST, NA, SMALL, 32 },
147 { 0x50, TLB, INST, NA, BOTH, 64 },
148 { 0x51, TLB, INST, NA, BOTH, 128 },
149 { 0x52, TLB, INST, NA, BOTH, 256 },
150 { 0x55, TLB, INST, FULLY, BOTH, 7 },
151 { 0x56, TLB, DATA0, 4, LARGE, 16 },
152 { 0x57, TLB, DATA0, 4, SMALL, 16 },
153 { 0x59, TLB, DATA0, FULLY, SMALL, 16 },
154 { 0x5A, TLB, DATA0, 4, LARGE, 32 },
155 { 0x5B, TLB, DATA, NA, BOTH, 64 },
156 { 0x5C, TLB, DATA, NA, BOTH, 128 },
157 { 0x5D, TLB, DATA, NA, BOTH, 256 },
165 { 0x76, TLB, INST, NA, BOTH, 8 },
180 { 0xB0, TLB, INST, 4, SMALL, 128 },
181 { 0xB1, TLB, INST, 4, LARGE, 8 },
182 { 0xB2, TLB, INST, 4, SMALL, 64 },
183 { 0xB3, TLB, DATA, 4, SMALL, 128 },
184 { 0xB4, TLB, DATA1, 4, SMALL, 256 },
185 { 0xB5, TLB, DATA1, 8, SMALL, 64 },
186 { 0xB6, TLB, DATA1, 8, SMALL, 128 },
187 { 0xBA, TLB, DATA1, 4, BOTH, 64 },
450 * Extract and publish TLB information from Leaf 2 descriptors.
465 case TLB: