Lines Matching refs:ctlreg
281 hsaddr_t port = 0,ctlreg,datareg;
292 ctlreg = A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_RAM_READCTL);
296 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) |
300 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) |
304 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) |
317 hsaddr_t port = 0,ctlreg,datareg;
328 ctlreg = A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_RAM_READCTL);
332 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) |
336 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) |
340 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) |
356 hsaddr_t ctlreg,datareg;
362 ctlreg = A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_TX_RF_READCTL);
370 WRITECSR(ctlreg,
379 WRITECSR(ctlreg,
383 WRITECSR(ctlreg,
387 WRITECSR(ctlreg,
399 WRITECSR(ctlreg,
403 WRITECSR(ctlreg,
407 WRITECSR(ctlreg,
423 WRITECSR(ctlreg,
433 WRITECSR(ctlreg,
451 hsaddr_t ctlreg,datareg;
457 ctlreg = A_BCM1480_HSP_REGISTER(port,R_BCM1480_HSP_RX_RF_READCTL);
466 WRITECSR(ctlreg,
470 WRITECSR(ctlreg,
474 WRITECSR(ctlreg,
484 WRITECSR(ctlreg,
488 WRITECSR(ctlreg,
492 WRITECSR(ctlreg,
502 WRITECSR(ctlreg,