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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/v850/

Lines Matching defs:op0

335 Multiply64 (int sign, unsigned long op0)
352 sign = (op0 ^ op1) & 0x80000000;
354 if (((signed long) op0) < 0)
355 op0 = - op0;
363 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
364 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
365 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
366 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
591 unsigned int op0, op1, result, z, s, cy, ov;
597 op0 = State.regs[ OP[0] ];
600 result = op0 + op1;
605 cy = (result < op0 || result < op1);
606 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
607 && (op0 & 0x80000000) != (result & 0x80000000));
623 unsigned int op0, op1, result, z, s, cy, ov;
630 op0 = temp;
632 result = op0 + op1;
637 cy = (result < op0 || result < op1);
638 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
639 && (op0 & 0x80000000) != (result & 0x80000000));
655 unsigned int op0, op1, result, z, s, cy, ov;
661 op0 = EXTEND16 (OP[2]);
663 result = op0 + op1;
668 cy = (result < op0 || result < op1);
669 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
670 && (op0 & 0x80000000) != (result & 0x80000000));
686 unsigned int op0, op1, result, z, s, cy, ov;
690 op0 = State.regs[ OP[0] ];
692 result = op1 - op0;
697 cy = (op1 < op0);
698 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
715 unsigned int op0, op1, result, z, s, cy, ov;
719 op0 = State.regs[ OP[0] ];
721 result = op0 - op1;
726 cy = (op0 < op1);
727 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
728 && (op0 & 0x80000000) != (result & 0x80000000));
783 unsigned int op0, op1, result, z, s, cy, ov;
787 op0 = State.regs[ OP[0] ];
789 result = op1 - op0;
794 cy = (op1 < op0);
795 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
811 unsigned int op0, op1, result, z, s, cy, ov;
817 op0 = temp;
819 result = op1 - op0;
824 cy = (op1 < op0);
825 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
854 unsigned int op0, op1, result, z, s, cy, ov, sat;
858 op0 = State.regs[ OP[0] ];
860 result = op0 + op1;
865 cy = (result < op0 || result < op1);
866 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
867 && (op0 & 0x80000000) != (result & 0x80000000));
891 unsigned int op0, op1, result, z, s, cy, ov, sat;
899 op0 = temp;
901 result = op0 + op1;
906 cy = (result < op0 || result < op1);
907 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
908 && (op0 & 0x80000000) != (result & 0x80000000));
932 unsigned int op0, op1, result, z, s, cy, ov, sat;
937 op0 = State.regs[ OP[0] ];
939 result = op1 - op0;
944 cy = (op1 < op0);
945 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
969 unsigned int op0, op1, result, z, s, cy, ov, sat;
976 op0 = temp;
978 result = op1 - op0;
983 cy = (op1 < op0);
984 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1009 unsigned int op0, op1, result, z, s, cy, ov, sat;
1014 op0 = State.regs[ OP[0] ];
1016 result = op0 - op1;
1021 cy = (result < op0);
1022 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1047 unsigned int op0, op1, result, z, s;
1052 op0 = State.regs[ OP[0] ];
1054 result = op0 & op1;
1100 unsigned int op0, op1, result, z, s, cy;
1103 op0 = OP[0];
1105 result = (signed)op1 >> op0;
1110 cy = (op1 & (1 << (op0 - 1)));
1126 unsigned int op0, op1, result, z, s, cy;
1130 op0 = State.regs[ OP[0] ] & 0x1f;
1132 result = (signed)op1 >> op0;
1137 cy = (op1 & (1 << (op0 - 1)));
1153 unsigned int op0, op1, result, z, s, cy;
1156 op0 = OP[0];
1158 result = op1 << op0;
1163 cy = (op1 & (1 << (32 - op0)));
1179 unsigned int op0, op1, result, z, s, cy;
1182 op0 = State.regs[ OP[0] ] & 0x1f;
1184 result = op1 << op0;
1189 cy = (op1 & (1 << (32 - op0)));
1205 unsigned int op0, op1, result, z, s, cy;
1208 op0 = OP[0];
1210 result = op1 >> op0;
1215 cy = (op1 & (1 << (op0 - 1)));
1231 unsigned int op0, op1, result, z, s, cy;
1234 op0 = State.regs[ OP[0] ] & 0x1f;
1236 result = op1 >> op0;
1241 cy = (op1 & (1 << (op0 - 1)));
1257 unsigned int op0, op1, result, z, s;
1262 op0 = State.regs[ OP[0] ];
1264 result = op0 | op1;
1283 unsigned int op0, op1, result, z, s;
1286 op0 = OP[2];
1288 result = op0 | op1;
1307 unsigned int op0, op1, result, z, s;
1312 op0 = State.regs[ OP[0] ];
1314 result = op0 & op1;
1357 unsigned int op0, op1, result, z, s;
1362 op0 = State.regs[ OP[0] ];
1364 result = op0 ^ op1;
1383 unsigned int op0, op1, result, z, s;
1386 op0 = OP[2];
1388 result = op0 ^ op1;
1407 unsigned int op0, result, z, s;
1411 op0 = State.regs[ OP[0] ];
1412 result = ~op0;
1431 unsigned int op0, op1, op2;
1435 op0 = State.regs[ OP[0] ];
1439 temp = load_mem (op0 + op2, 1);
1444 store_mem (op0 + op2, 1, temp);
1454 unsigned int op0, op1, op2;
1458 op0 = State.regs[ OP[0] ];
1462 temp = load_mem (op0 + op2, 1);
1467 store_mem (op0 + op2, 1, temp);
1477 unsigned int op0, op1, op2;
1481 op0 = State.regs[ OP[0] ];
1485 temp = load_mem (op0 + op2, 1);
1490 store_mem (op0 + op2, 1, temp);
1500 unsigned int op0, op1, op2;
1504 op0 = State.regs[ OP[0] ];
1508 temp = load_mem (op0 + op2, 1);