#
b524f8fb |
|
22-Jul-2022 |
Adrian Fiergolski <adrian.fiergolski@fastree3d.com> |
fpga: zynqmp: support loading encrypted bitfiles Add supporting new compatible string "u-boot,zynqmp-fpga-enc" to handle loading encrypted bitfiles. This feature requires encrypted FSBL, as according to UG1085: "The CSU automatically locks out the AES key, stored in either BBRAM or eFUSEs, as a key source to the AES engine if the FSBL is not encrypted. This prevents using the BBRAM or eFUSE as the key source to the AES engine during run-time applications." Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-14-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
a3a1afb7 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: zynqmp: support loading authenticated images Add supporting new compatible string "u-boot,zynqmp-fpga-ddrauth" to handle loading authenticated images (DDR). Based on solution by Jorge Ramirez-Ortiz <jorge@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Link: https://lore.kernel.org/r/20220722141614.297383-13-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
3e78481d |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: xilinx: pass compatible flags to load() callback These flags may be used to check whether an FPGA driver is able to load a particular FPGA bitstream image. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-10-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
7a9a0df8 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: xilinx: pass compatible flags to xilinx_load() This flag is used to check whether a Xilinx FPGA driver is able to load a particular FPGA bitstream image. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-6-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
24307b06 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: zynqmp: add str2flags call Add a call to convert FPGA "compatible" string to a binary flag. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-5-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
d7fcbfc1 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: xilinx: add bitstream flags to driver desc Store a set of supported bitstream types in xilinx_desc structure. It will be used to determine whether an FPGA image is able to be loaded with a given driver. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-4-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
f18adf10 |
|
22-Jul-2022 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
fpga: xilinx: add missed identifier names Function definition arguments should also have identifier names. Add missed ones to struct xilinx_fpga_op callbacks, unifying code. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-3-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
a18d09ea |
|
31-May-2018 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: zynqmp: Add secure bitstream loading for ZynqMP This patch adds support for loading secure bitstreams on ZynqMP platforms. The secure bitstream images has to be generated using Xilinx bootgen tool. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
1a897668 |
|
14-Mar-2014 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: Added support to load bit stream from SD/MMC Added support to load a bitstream image in chunks by reading it in chunks from SD/MMC. Command format: loadfs [dev] [address] [image size] [blocksize] <interface> [<dev[:part]>] <filename> Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
7a78bd26 |
|
02-May-2014 |
Michal Simek <michal.simek@amd.com> |
fpga: Define bitstream type based on command selection Clean up partial, full and compressed bitstream handling. U-Boot supports full bitstream loading and partial based on detection which is not 100% correct. Extending fpga_load/fpga_loadbitstream() with one more argument which stores bitstream type. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
14cfc4f3 |
|
13-Mar-2014 |
Michal Simek <michal.simek@amd.com> |
fpga: xilinx: Simplify load/dump/info function handling Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
2df9d5c4 |
|
12-Mar-2014 |
Michal Simek <michal.simek@amd.com> |
fpga: xilinx: Fix the rest of CamelCases No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
f8c1be98 |
|
12-Mar-2014 |
Michal Simek <michal.simek@amd.com> |
fpga: xilinx: Avoid CamelCase for in Xilinx_desc No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
d9071ce0 |
|
13-Mar-2014 |
Michal Simek <michal.simek@amd.com> |
fpga: virtex2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
2a6e3869 |
|
13-Mar-2014 |
Michal Simek <michal.simek@amd.com> |
fpga: spartan3: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
b625b9ae |
|
13-Mar-2014 |
Michal Simek <michal.simek@amd.com> |
fpga: spartan2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
b03b25ca |
|
01-May-2013 |
Michal Simek <michal.simek@amd.com> |
fpga: Remove all CONFIG_SYS_* fpga related options All these macros are completely unused by any code. CONFIG_FPGA is not a bitfield anymore. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
6631db47 |
|
26-Apr-2013 |
Michal Simek <michal.simek@amd.com> |
fpga: Check device name against bitstream name Ensure that wrong bitstream won't be loaded to current device. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
d5dae85f |
|
22-Apr-2013 |
Michal Simek <michal.simek@amd.com> |
fpga: zynq: Add support for loading bitstream Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
e6a857da |
|
30-Jul-2011 |
Wolfgang Denk <wd@denx.de> |
fpga: constify to fix build warning Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de> |
#
89083346 |
|
30-Oct-2009 |
Wolfgang Wegner <w.wegner@astro-kom.de> |
add block write function to spartan3 slave serial load Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de> |
#
6385b281 |
|
21-Sep-2009 |
Peter Tyser <ptyser@xes-inc.com> |
fpga: Remove relocation fixups PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
6d0f6bcf |
|
16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
53677ef1 |
|
20-May-2008 |
Wolfgang Denk <wd@denx.de> |
Big white-space cleanup. This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
0133502e |
|
27-Dec-2007 |
Matthias Fuchs <matthias.fuchs@esd-electronics.com> |
Improve configuration of FPGA subsystem This patch removes the FPGA subsystem configuration through the CONFIG_FPGA bitmask configuration option. See README for the new options: CONFIG_FPGA, CONFIG_FPGA_<vendor>, CONFIG_FPGA_<family> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> |
#
875c7893 |
|
25-Sep-2005 |
Wolfgang Denk <wd@denx.de> |
Add Xilinx Spartan3 family FPGA support Patch by Kurt Stremerch, 14 February 2005 |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
Initial revision |
#
26e054c9 |
|
05-Aug-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
a18d09ea |
|
31-May-2018 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: zynqmp: Add secure bitstream loading for ZynqMP This patch adds support for loading secure bitstreams on ZynqMP platforms. The secure bitstream images has to be generated using Xilinx bootgen tool. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6b245014 |
|
13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
1a897668 |
|
14-Mar-2014 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: Added support to load bit stream from SD/MMC Added support to load a bitstream image in chunks by reading it in chunks from SD/MMC. Command format: loadfs [dev] [address] [image size] [blocksize] <interface> [<dev[:part]>] <filename> Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
7a78bd26 |
|
02-May-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: Define bitstream type based on command selection Clean up partial, full and compressed bitstream handling. U-Boot supports full bitstream loading and partial based on detection which is not 100% correct. Extending fpga_load/fpga_loadbitstream() with one more argument which stores bitstream type. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
14cfc4f3 |
|
13-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: xilinx: Simplify load/dump/info function handling Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
2df9d5c4 |
|
12-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: xilinx: Fix the rest of CamelCases No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
f8c1be98 |
|
12-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: xilinx: Avoid CamelCase for in Xilinx_desc No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
d9071ce0 |
|
13-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: virtex2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
2a6e3869 |
|
13-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: spartan3: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
b625b9ae |
|
13-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: spartan2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
b03b25ca |
|
01-May-2013 |
Michal Simek <michal.simek@xilinx.com> |
fpga: Remove all CONFIG_SYS_* fpga related options All these macros are completely unused by any code. CONFIG_FPGA is not a bitfield anymore. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
6631db47 |
|
26-Apr-2013 |
Michal Simek <michal.simek@xilinx.com> |
fpga: Check device name against bitstream name Ensure that wrong bitstream won't be loaded to current device. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
d5dae85f |
|
22-Apr-2013 |
Michal Simek <michal.simek@xilinx.com> |
fpga: zynq: Add support for loading bitstream Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
e6a857da |
|
30-Jul-2011 |
Wolfgang Denk <wd@denx.de> |
fpga: constify to fix build warning Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de> |
#
89083346 |
|
30-Oct-2009 |
Wolfgang Wegner <w.wegner@astro-kom.de> |
add block write function to spartan3 slave serial load Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de> |
#
6385b281 |
|
21-Sep-2009 |
Peter Tyser <ptyser@xes-inc.com> |
fpga: Remove relocation fixups PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
6d0f6bcf |
|
16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
53677ef1 |
|
20-May-2008 |
Wolfgang Denk <wd@denx.de> |
Big white-space cleanup. This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
0133502e |
|
27-Dec-2007 |
Matthias Fuchs <matthias.fuchs@esd-electronics.com> |
Improve configuration of FPGA subsystem This patch removes the FPGA subsystem configuration through the CONFIG_FPGA bitmask configuration option. See README for the new options: CONFIG_FPGA, CONFIG_FPGA_<vendor>, CONFIG_FPGA_<family> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> |
#
875c7893 |
|
25-Sep-2005 |
Wolfgang Denk <wd@pollux.(none)> |
Add Xilinx Spartan3 family FPGA support Patch by Kurt Stremerch, 14 February 2005 |
#
c609719b |
|
02-Nov-2002 |
wdenk <wdenk> |
Initial revision |
#
a18d09ea |
|
31-May-2018 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: zynqmp: Add secure bitstream loading for ZynqMP This patch adds support for loading secure bitstreams on ZynqMP platforms. The secure bitstream images has to be generated using Xilinx bootgen tool. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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6b245014 |
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13-Jan-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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1a897668 |
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14-Mar-2014 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
fpga: Added support to load bit stream from SD/MMC Added support to load a bitstream image in chunks by reading it in chunks from SD/MMC. Command format: loadfs [dev] [address] [image size] [blocksize] <interface> [<dev[:part]>] <filename> Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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7a78bd26 |
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02-May-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: Define bitstream type based on command selection Clean up partial, full and compressed bitstream handling. U-Boot supports full bitstream loading and partial based on detection which is not 100% correct. Extending fpga_load/fpga_loadbitstream() with one more argument which stores bitstream type. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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14cfc4f3 |
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13-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: xilinx: Simplify load/dump/info function handling Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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2df9d5c4 |
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12-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: xilinx: Fix the rest of CamelCases No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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f8c1be98 |
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12-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: xilinx: Avoid CamelCase for in Xilinx_desc No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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d9071ce0 |
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13-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: virtex2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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2a6e3869 |
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13-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: spartan3: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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b625b9ae |
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13-Mar-2014 |
Michal Simek <michal.simek@xilinx.com> |
fpga: spartan2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
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b03b25ca |
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01-May-2013 |
Michal Simek <michal.simek@xilinx.com> |
fpga: Remove all CONFIG_SYS_* fpga related options All these macros are completely unused by any code. CONFIG_FPGA is not a bitfield anymore. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
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6631db47 |
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26-Apr-2013 |
Michal Simek <michal.simek@xilinx.com> |
fpga: Check device name against bitstream name Ensure that wrong bitstream won't be loaded to current device. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
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d5dae85f |
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22-Apr-2013 |
Michal Simek <michal.simek@xilinx.com> |
fpga: zynq: Add support for loading bitstream Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
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e6a857da |
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30-Jul-2011 |
Wolfgang Denk <wd@denx.de> |
fpga: constify to fix build warning Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
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89083346 |
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30-Oct-2009 |
Wolfgang Wegner <w.wegner@astro-kom.de> |
add block write function to spartan3 slave serial load Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
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6385b281 |
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21-Sep-2009 |
Peter Tyser <ptyser@xes-inc.com> |
fpga: Remove relocation fixups PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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6d0f6bcf |
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16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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53677ef1 |
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20-May-2008 |
Wolfgang Denk <wd@denx.de> |
Big white-space cleanup. This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
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0133502e |
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27-Dec-2007 |
Matthias Fuchs <matthias.fuchs@esd-electronics.com> |
Improve configuration of FPGA subsystem This patch removes the FPGA subsystem configuration through the CONFIG_FPGA bitmask configuration option. See README for the new options: CONFIG_FPGA, CONFIG_FPGA_<vendor>, CONFIG_FPGA_<family> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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875c7893 |
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25-Sep-2005 |
Wolfgang Denk <wd@pollux.(none)> |
Add Xilinx Spartan3 family FPGA support Patch by Kurt Stremerch, 14 February 2005
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c609719b |
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02-Nov-2002 |
wdenk <wdenk> |
Initial revision
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